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Add ice40 box files
[yosys.git]
/
techlibs
/
ice40
/
cells_box.v
1
(* abc_box_id = 1 *)
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module SB_CARRY (output CO, input CI, I0, I1);
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assign CO = (I0 && I1) || ((I0 || I1) && CI);
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endmodule
5