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abc9: generate $abc9_holes design instead of <name>$holes
[yosys.git] / techlibs / ice40 / cells_sim.v
1 `timescale 1ps / 1ps
2 `define SB_DFF_REG reg Q = 0
3 // `define SB_DFF_REG reg Q
4
5 // SiliconBlue IO Cells
6
7 module SB_IO (
8 inout PACKAGE_PIN,
9 input LATCH_INPUT_VALUE,
10 input CLOCK_ENABLE,
11 input INPUT_CLK,
12 input OUTPUT_CLK,
13 input OUTPUT_ENABLE,
14 input D_OUT_0,
15 input D_OUT_1,
16 output D_IN_0,
17 output D_IN_1
18 );
19 parameter [5:0] PIN_TYPE = 6'b000000;
20 parameter [0:0] PULLUP = 1'b0;
21 parameter [0:0] NEG_TRIGGER = 1'b0;
22 parameter IO_STANDARD = "SB_LVCMOS";
23
24 `ifndef BLACKBOX
25 reg dout, din_0, din_1;
26 reg din_q_0, din_q_1;
27 reg dout_q_0, dout_q_1;
28 reg outena_q;
29
30 // IO tile generates a constant 1'b1 internally if global_cen is not connected
31 wire clken_pulled = CLOCK_ENABLE || CLOCK_ENABLE === 1'bz;
32 reg clken_pulled_ri;
33 reg clken_pulled_ro;
34
35 generate if (!NEG_TRIGGER) begin
36 always @(posedge INPUT_CLK) clken_pulled_ri <= clken_pulled;
37 always @(posedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN;
38 always @(negedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN;
39 always @(posedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled;
40 always @(posedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0;
41 always @(negedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1;
42 always @(posedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE;
43 end else begin
44 always @(negedge INPUT_CLK) clken_pulled_ri <= clken_pulled;
45 always @(negedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN;
46 always @(posedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN;
47 always @(negedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled;
48 always @(negedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0;
49 always @(posedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1;
50 always @(negedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE;
51 end endgenerate
52
53 always @* begin
54 if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
55 din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
56 din_1 = din_q_1;
57 end
58
59 // work around simulation glitches on dout in DDR mode
60 reg outclk_delayed_1;
61 reg outclk_delayed_2;
62 always @* outclk_delayed_1 <= OUTPUT_CLK;
63 always @* outclk_delayed_2 <= outclk_delayed_1;
64
65 always @* begin
66 if (PIN_TYPE[3])
67 dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
68 else
69 dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
70 end
71
72 assign D_IN_0 = din_0, D_IN_1 = din_1;
73
74 generate
75 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
76 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
77 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
78 endgenerate
79 `endif
80 `ifdef TIMING
81 specify
82 (INPUT_CLK => D_IN_0) = (0:0:0, 0:0:0);
83 (INPUT_CLK => D_IN_1) = (0:0:0, 0:0:0);
84 (PACKAGE_PIN => D_IN_0) = (0:0:0, 0:0:0);
85 (OUTPUT_CLK => PACKAGE_PIN) = (0:0:0, 0:0:0);
86 (D_OUT_0 => PACKAGE_PIN) = (0:0:0, 0:0:0);
87 (OUTPUT_ENABLE => PACKAGE_PIN) = (0:0:0, 0:0:0);
88
89 $setuphold(posedge OUTPUT_CLK, posedge D_OUT_0, 0:0:0, 0:0:0);
90 $setuphold(posedge OUTPUT_CLK, negedge D_OUT_0, 0:0:0, 0:0:0);
91 $setuphold(negedge OUTPUT_CLK, posedge D_OUT_1, 0:0:0, 0:0:0);
92 $setuphold(negedge OUTPUT_CLK, negedge D_OUT_1, 0:0:0, 0:0:0);
93 $setuphold(negedge OUTPUT_CLK, posedge D_OUT_0, 0:0:0, 0:0:0);
94 $setuphold(negedge OUTPUT_CLK, negedge D_OUT_0, 0:0:0, 0:0:0);
95 $setuphold(posedge OUTPUT_CLK, posedge D_OUT_1, 0:0:0, 0:0:0);
96 $setuphold(posedge OUTPUT_CLK, negedge D_OUT_1, 0:0:0, 0:0:0);
97 $setuphold(posedge INPUT_CLK, posedge CLOCK_ENABLE, 0:0:0, 0:0:0);
98 $setuphold(posedge INPUT_CLK, negedge CLOCK_ENABLE, 0:0:0, 0:0:0);
99 $setuphold(posedge OUTPUT_CLK, posedge CLOCK_ENABLE, 0:0:0, 0:0:0);
100 $setuphold(posedge OUTPUT_CLK, negedge CLOCK_ENABLE, 0:0:0, 0:0:0);
101 $setuphold(posedge INPUT_CLK, posedge PACKAGE_PIN, 0:0:0, 0:0:0);
102 $setuphold(posedge INPUT_CLK, negedge PACKAGE_PIN, 0:0:0, 0:0:0);
103 $setuphold(negedge INPUT_CLK, posedge PACKAGE_PIN, 0:0:0, 0:0:0);
104 $setuphold(negedge INPUT_CLK, negedge PACKAGE_PIN, 0:0:0, 0:0:0);
105 $setuphold(posedge OUTPUT_CLK, posedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
106 $setuphold(posedge OUTPUT_CLK, negedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
107 $setuphold(negedge OUTPUT_CLK, posedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
108 $setuphold(negedge OUTPUT_CLK, negedge OUTPUT_ENABLE, 0:0:0, 0:0:0);
109 endspecify
110 `endif
111 endmodule
112
113 module SB_GB_IO (
114 inout PACKAGE_PIN,
115 output GLOBAL_BUFFER_OUTPUT,
116 input LATCH_INPUT_VALUE,
117 input CLOCK_ENABLE,
118 input INPUT_CLK,
119 input OUTPUT_CLK,
120 input OUTPUT_ENABLE,
121 input D_OUT_0,
122 input D_OUT_1,
123 output D_IN_0,
124 output D_IN_1
125 );
126 parameter [5:0] PIN_TYPE = 6'b000000;
127 parameter [0:0] PULLUP = 1'b0;
128 parameter [0:0] NEG_TRIGGER = 1'b0;
129 parameter IO_STANDARD = "SB_LVCMOS";
130
131 assign GLOBAL_BUFFER_OUTPUT = PACKAGE_PIN;
132
133 SB_IO #(
134 .PIN_TYPE(PIN_TYPE),
135 .PULLUP(PULLUP),
136 .NEG_TRIGGER(NEG_TRIGGER),
137 .IO_STANDARD(IO_STANDARD)
138 ) IO (
139 .PACKAGE_PIN(PACKAGE_PIN),
140 .LATCH_INPUT_VALUE(LATCH_INPUT_VALUE),
141 .CLOCK_ENABLE(CLOCK_ENABLE),
142 .INPUT_CLK(INPUT_CLK),
143 .OUTPUT_CLK(OUTPUT_CLK),
144 .OUTPUT_ENABLE(OUTPUT_ENABLE),
145 .D_OUT_0(D_OUT_0),
146 .D_OUT_1(D_OUT_1),
147 .D_IN_0(D_IN_0),
148 .D_IN_1(D_IN_1)
149 );
150 endmodule
151
152 module SB_GB (
153 input USER_SIGNAL_TO_GLOBAL_BUFFER,
154 output GLOBAL_BUFFER_OUTPUT
155 );
156 assign GLOBAL_BUFFER_OUTPUT = USER_SIGNAL_TO_GLOBAL_BUFFER;
157 `ifdef TIMING
158 specify
159 (USER_SIGNAL_TO_GLOBAL_BUFFER => GLOBAL_BUFFER_OUTPUT) = (0:0:0, 0:0:0);
160 endspecify
161 `endif
162 endmodule
163
164 // SiliconBlue Logic Cells
165
166 (* abc9_lut=1, lib_whitebox *)
167 module SB_LUT4 (output O, input I0, I1, I2, I3);
168 parameter [15:0] LUT_INIT = 0;
169 wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
170 wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
171 wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];
172 assign O = I0 ? s1[1] : s1[0];
173 `ifdef ICE40_HX
174 specify
175 // https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L80
176 (I0 => O) = (449, 386);
177 // https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L83
178 (I1 => O) = (400, 379);
179 // https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L86
180 (I2 => O) = (379, 351);
181 // https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L88
182 (I3 => O) = (316, 288);
183 endspecify
184 `endif
185 `ifdef ICE40_LP
186 specify
187 // https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L80
188 (I0 => O) = (662, 569);
189 // https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L83
190 (I1 => O) = (589, 558);
191 // https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L86
192 (I2 => O) = (558, 517);
193 // https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L88
194 (I3 => O) = (465, 423);
195 endspecify
196 `endif
197 `ifdef ICE40_U
198 specify
199 // https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L92
200 (I0 => O) = (1245, 1285);
201 // https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L95
202 (I1 => O) = (1179, 1232);
203 // https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L98
204 (I2 => O) = (1179, 1205);
205 // https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L100
206 (I3 => O) = (861, 874);
207 endspecify
208 `endif
209 endmodule
210
211 (* lib_whitebox *)
212 module SB_CARRY (output CO, input I0, I1, CI);
213 assign CO = (I0 && I1) || ((I0 || I1) && CI);
214 `ifdef ICE40_HX
215 specify
216 // https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L79
217 (CI => CO) = (126, 105);
218 // https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L82
219 (I0 => CO) = (259, 245);
220 // https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L85
221 (I1 => CO) = (231, 133);
222 endspecify
223 `endif
224 `ifdef ICE40_LP
225 specify
226 // https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L79
227 (CI => CO) = (186, 155);
228 // https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L82
229 (I0 => CO) = (382, 362);
230 // https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L85
231 (I0 => CO) = (341, 196);
232 endspecify
233 `endif
234 `ifdef ICE40_U
235 specify
236 // https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L91
237 (CI => CO) = (278, 278);
238 // https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L94
239 (I0 => CO) = (675, 662);
240 // https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L97
241 (I0 => CO) = (609, 358);
242 endspecify
243 `endif
244 endmodule
245
246 // Positive Edge SiliconBlue FF Cells
247
248 (* abc9_flop, lib_whitebox *)
249 module SB_DFF (
250 output `SB_DFF_REG,
251 input C, D
252 );
253 always @(posedge C)
254 Q <= D;
255 `ifdef ICE40_HX
256 specify
257 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
258 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
259 $setup(D, posedge C, 470 - 449);
260 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
261 (posedge C => (Q : D)) = 540;
262 endspecify
263 `endif
264 `ifdef ICE40_LP
265 specify
266 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
267 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
268 $setup(D, posedge C, 693 - 662);
269 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
270 (posedge C => (Q : D)) = 796;
271 endspecify
272 `endif
273 `ifdef ICE40_U
274 specify
275 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
276 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
277 $setup(D, posedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
278 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
279 (posedge C => (Q : D)) = 1391;
280 endspecify
281 `endif
282 endmodule
283
284 (* abc9_flop, lib_whitebox *)
285 module SB_DFFE (
286 output `SB_DFF_REG,
287 input C, E, D
288 );
289 always @(posedge C)
290 if (E)
291 Q <= D;
292 `ifdef ICE40_HX
293 specify
294 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
295 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
296 $setup(D, posedge C &&& E, 470 - 449);
297 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
298 $setup(E, posedge C, 0);
299 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
300 if (E) (posedge C => (Q : D)) = 540;
301 endspecify
302 `endif
303 `ifdef ICE40_LP
304 specify
305 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
306 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
307 $setup(D, posedge C &&& E, 693 - 662);
308 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
309 $setup(E, posedge C, 0);
310 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
311 if (E) (posedge C => (Q : D)) = 796;
312 endspecify
313 `endif
314 `ifdef ICE40_U
315 specify
316 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
317 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
318 $setup(D, posedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
319 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
320 $setup(E, posedge C, 0);
321 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
322 if (E) (posedge C => (Q : D)) = 1391;
323 endspecify
324 `endif
325 endmodule
326
327 (* abc9_flop, lib_whitebox *)
328 module SB_DFFSR (
329 output `SB_DFF_REG,
330 input C, R, D
331 );
332 always @(posedge C)
333 if (R)
334 Q <= 0;
335 else
336 Q <= D;
337 `ifdef ICE40_HX
338 specify
339 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
340 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
341 $setup(D, posedge C, 470 - 449);
342 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
343 $setup(R, posedge C, 203);
344 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
345 if ( R) (posedge C => (Q : 1'b0)) = 540;
346 if (!R) (posedge C => (Q : D)) = 540;
347 endspecify
348 `endif
349 `ifdef ICE40_LP
350 specify
351 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
352 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
353 $setup(D, posedge C, 693 - 662);
354 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
355 $setup(R, posedge C, 299);
356 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
357 if ( R) (posedge C => (Q : 1'b0)) = 796;
358 if (!R) (posedge C => (Q : D)) = 796;
359 endspecify
360 `endif
361 `ifdef ICE40_U
362 specify
363 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
364 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
365 $setup(D, posedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
366 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
367 $setup(R, posedge C, 530);
368 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
369 if ( R) (posedge C => (Q : 1'b0)) = 1391;
370 if (!R) (posedge C => (Q : D)) = 1391;
371 endspecify
372 `endif
373 endmodule
374
375 module SB_DFFR (
376 output `SB_DFF_REG,
377 input C, R, D
378 );
379 always @(posedge C, posedge R)
380 if (R)
381 Q <= 0;
382 else
383 Q <= D;
384 `ifdef ICE40_HX
385 specify
386 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
387 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
388 $setup(D, posedge C, 470 - 449);
389 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
390 $setup(negedge R, posedge C, 160);
391 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
392 (posedge R => (Q : 1'b0)) = 599;
393 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
394 if (!R) (posedge C => (Q : D)) = 540;
395 endspecify
396 `endif
397 `ifdef ICE40_LP
398 specify
399 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
400 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
401 $setup(D, posedge C, 693 - 662);
402 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
403 $setup(negedge R, posedge C, 235);
404 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
405 (posedge R => (Q : 1'b0)) = 883;
406 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
407 if (!R) (posedge C => (Q : D)) = 796;
408 endspecify
409 `endif
410 `ifdef ICE40_U
411 specify
412 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
413 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
414 $setup(D, posedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
415 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
416 $setup(negedge R, posedge C, 424);
417 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
418 (posedge R => (Q : 1'b0)) = 1589;
419 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
420 if (!R) (posedge C => (Q : D)) = 1391;
421 endspecify
422 `endif
423 endmodule
424
425 (* abc9_flop, lib_whitebox *)
426 module SB_DFFSS (
427 output `SB_DFF_REG,
428 input C, S, D
429 );
430 always @(posedge C)
431 if (S)
432 Q <= 1;
433 else
434 Q <= D;
435 `ifdef ICE40_HX
436 specify
437 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
438 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
439 $setup(D, posedge C, 470 - 449);
440 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
441 $setup(S, posedge C, 203);
442 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
443 if ( S) (posedge C => (Q : 1'b1)) = 540;
444 if (!S) (posedge C => (Q : D)) = 540;
445 endspecify
446 `endif
447 `ifdef ICE40_LP
448 specify
449 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
450 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
451 $setup(D, posedge C, 693 - 662);
452 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
453 $setup(S, posedge C, 299);
454 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
455 if ( S) (posedge C => (Q : 1'b1)) = 796;
456 if (!S) (posedge C => (Q : D)) = 796;
457 endspecify
458 `endif
459 `ifdef ICE40_U
460 specify
461 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
462 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
463 $setup(D, posedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
464 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
465 $setup(S, posedge C, 530);
466 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
467 if ( S) (posedge C => (Q : 1'b1)) = 1391;
468 if (!S) (posedge C => (Q : D)) = 1391;
469 endspecify
470 `endif
471 endmodule
472
473 module SB_DFFS (
474 output `SB_DFF_REG,
475 input C, S, D
476 );
477 always @(posedge C, posedge S)
478 if (S)
479 Q <= 1;
480 else
481 Q <= D;
482 `ifdef ICE40_HX
483 specify
484 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
485 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
486 $setup(D, posedge C, 470 - 449);
487 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
488 $setup(negedge S, posedge C, 160);
489 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
490 (posedge S => (Q : 1'b1)) = 599;
491 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
492 if (!S) (posedge C => (Q : D)) = 540;
493 endspecify
494 `endif
495 `ifdef ICE40_LP
496 specify
497 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
498 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
499 $setup(D, posedge C, 693 - 662);
500 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
501 $setup(negedge S, posedge C, 235);
502 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
503 (posedge S => (Q : 1'b1)) = 883;
504 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
505 if (!S) (posedge C => (Q : D)) = 796;
506 endspecify
507 `endif
508 `ifdef ICE40_U
509 specify
510 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
511 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
512 $setup(D, posedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
513 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
514 $setup(negedge S, posedge C, 424);
515 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
516 (posedge S => (Q : 1'b1)) = 1589;
517 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
518 if (!S) (posedge C => (Q : D)) = 1391;
519 endspecify
520 `endif
521 endmodule
522
523 (* abc9_flop, lib_whitebox *)
524 module SB_DFFESR (
525 output `SB_DFF_REG,
526 input C, E, R, D
527 );
528 always @(posedge C)
529 if (E) begin
530 if (R)
531 Q <= 0;
532 else
533 Q <= D;
534 end
535 `ifdef ICE40_HX
536 specify
537 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
538 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
539 $setup(D, posedge C &&& E && !R, 470 - 449);
540 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
541 $setup(E, posedge C, 0);
542 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
543 $setup(R, posedge C &&& E, 203);
544 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
545 if (E && R) (posedge C => (Q : 1'b0)) = 540;
546 if (E && !R) (posedge C => (Q : D)) = 540;
547 endspecify
548 `endif
549 `ifdef ICE40_LP
550 specify
551 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
552 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
553 $setup(D, posedge C &&& E && !R, 693 - 662);
554 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
555 $setup(E, posedge C, 0);
556 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
557 $setup(R, posedge C &&& E, 299);
558 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
559 if (E && R) (posedge C => (Q : 1'b0)) = 796;
560 if (E && !R) (posedge C => (Q : D)) = 796;
561 endspecify
562 `endif
563 `ifdef ICE40_U
564 specify
565 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
566 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
567 $setup(D, posedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
568 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
569 $setup(E, posedge C, 0);
570 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
571 $setup(R, posedge C &&& E, 530);
572 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
573 if (E && R) (posedge C => (Q : 1'b0)) = 1391;
574 if (E && !R) (posedge C => (Q : D)) = 1391;
575 endspecify
576 `endif
577 endmodule
578
579 module SB_DFFER (
580 output `SB_DFF_REG,
581 input C, E, R, D
582 );
583 always @(posedge C, posedge R)
584 if (R)
585 Q <= 0;
586 else if (E)
587 Q <= D;
588 `ifdef ICE40_HX
589 specify
590 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
591 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
592 $setup(D, posedge C &&& E, 470 - 449);
593 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
594 $setup(E, posedge C, 0);
595 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
596 $setup(negedge R, posedge C, 160);
597 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
598 (posedge R => (Q : 1'b0)) = 599;
599 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
600 if (E && !R) (posedge C => (Q : D)) = 540;
601 endspecify
602 `endif
603 `ifdef ICE40_LP
604 specify
605 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
606 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
607 $setup(D, posedge C &&& E, 693 - 662);
608 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
609 $setup(E, posedge C, 0);
610 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
611 $setup(negedge R, posedge C, 235);
612 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
613 (posedge R => (Q : 1'b0)) = 883;
614 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
615 if (E && !R) (posedge C => (Q : D)) = 796;
616 endspecify
617 `endif
618 `ifdef ICE40_U
619 specify
620 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
621 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
622 $setup(D, posedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
623 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
624 $setup(E, posedge C, 0);
625 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
626 $setup(negedge R, posedge C, 424);
627 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
628 (posedge R => (Q : 1'b0)) = 1589;
629 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
630 if (E && !R) (posedge C => (Q : D)) = 1391;
631 endspecify
632 `endif
633 endmodule
634
635 (* abc9_flop, lib_whitebox *)
636 module SB_DFFESS (
637 output `SB_DFF_REG,
638 input C, E, S, D
639 );
640 always @(posedge C)
641 if (E) begin
642 if (S)
643 Q <= 1;
644 else
645 Q <= D;
646 end
647 `ifdef ICE40_HX
648 specify
649 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
650 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
651 $setup(D, posedge C &&& E && !S, 470 - 449);
652 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
653 $setup(E, posedge C, 0);
654 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
655 $setup(S, posedge C &&& E, 203);
656 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
657 if (E && S) (posedge C => (Q : 1'b1)) = 540;
658 if (E && !S) (posedge C => (Q : D)) = 540;
659 endspecify
660 `endif
661 `ifdef ICE40_LP
662 specify
663 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
664 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
665 $setup(D, posedge C &&& E && !S, 693 - 662);
666 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
667 $setup(E, posedge C, 0);
668 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
669 $setup(S, posedge C &&& E, 299);
670 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
671 if (E && S) (posedge C => (Q : 1'b1)) = 796;
672 if (E && !S) (posedge C => (Q : D)) = 796;
673 endspecify
674 `endif
675 `ifdef ICE40_U
676 specify
677 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
678 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
679 $setup(D, posedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
680 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
681 $setup(E, posedge C, 0);
682 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
683 $setup(S, posedge C &&& E, 530);
684 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
685 if (E && S) (posedge C => (Q : 1'b1)) = 1391;
686 if (E && !S) (posedge C => (Q : D)) = 1391;
687 endspecify
688 `endif
689 endmodule
690
691 module SB_DFFES (
692 output `SB_DFF_REG,
693 input C, E, S, D
694 );
695 always @(posedge C, posedge S)
696 if (S)
697 Q <= 1;
698 else if (E)
699 Q <= D;
700 `ifdef ICE40_HX
701 specify
702 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
703 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
704 $setup(D, posedge C &&& E, 470 - 449);
705 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
706 $setup(E, posedge C, 0);
707 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
708 $setup(posedge S, posedge C, 160);
709 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
710 (posedge S => (Q : 1'b1)) = 599;
711 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
712 if (E && !S) (posedge C => (Q : D)) = 540;
713 endspecify
714 `endif
715 `ifdef ICE40_LP
716 specify
717 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
718 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
719 $setup(D, posedge C &&& E, 693 - 662);
720 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
721 $setup(E, posedge C, 0);
722 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
723 $setup(posedge S, posedge C, 235);
724 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
725 (posedge S => (Q : 1'b1)) = 883;
726 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
727 if (E && !S) (posedge C => (Q : D)) = 796;
728 endspecify
729 `endif
730 `ifdef ICE40_U
731 specify
732 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
733 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
734 $setup(D, posedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
735 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
736 $setup(E, posedge C, 0);
737 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
738 $setup(posedge S, posedge C, 424);
739 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
740 (posedge S => (Q : 1'b1)) = 1589;
741 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
742 if (E && !S) (posedge C => (Q : D)) = 1391;
743 endspecify
744 `endif
745 endmodule
746
747 // Negative Edge SiliconBlue FF Cells
748
749 (* abc9_flop, lib_whitebox *)
750 module SB_DFFN (
751 output `SB_DFF_REG,
752 input C, D
753 );
754 always @(negedge C)
755 Q <= D;
756 `ifdef ICE40_HX
757 specify
758 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
759 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
760 $setup(D, negedge C, 470 - 449);
761 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
762 (negedge C => (Q : D)) = 540;
763 endspecify
764 `endif
765 `ifdef ICE40_LP
766 specify
767 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
768 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
769 $setup(D, negedge C, 693 - 662);
770 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
771 (negedge C => (Q : D)) = 796;
772 endspecify
773 `endif
774 `ifdef ICE40_U
775 specify
776 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
777 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
778 $setup(D, negedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
779 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
780 (negedge C => (Q : D)) = 1391;
781 endspecify
782 `endif
783 endmodule
784
785 (* abc9_flop, lib_whitebox *)
786 module SB_DFFNE (
787 output `SB_DFF_REG,
788 input C, E, D
789 );
790 always @(negedge C)
791 if (E)
792 Q <= D;
793 `ifdef ICE40_HX
794 specify
795 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
796 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
797 $setup(D, negedge C &&& E, 470 - 449);
798 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
799 $setup(E, negedge C, 0);
800 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
801 if (E) (negedge C => (Q : D)) = 540;
802 endspecify
803 `endif
804 `ifdef ICE40_LP
805 specify
806 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
807 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
808 $setup(D, negedge C &&& E, 693 - 662);
809 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
810 $setup(E, negedge C, 0);
811 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
812 if (E) (negedge C => (Q : D)) = 796;
813 endspecify
814 `endif
815 `ifdef ICE40_U
816 specify
817 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
818 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
819 $setup(D, negedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
820 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
821 $setup(E, negedge C, 0);
822 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
823 if (E) (negedge C => (Q : D)) = 1391;
824 endspecify
825 `endif
826 endmodule
827
828 (* abc9_flop, lib_whitebox *)
829 module SB_DFFNSR (
830 output `SB_DFF_REG,
831 input C, R, D
832 );
833 always @(negedge C)
834 if (R)
835 Q <= 0;
836 else
837 Q <= D;
838 `ifdef ICE40_HX
839 specify
840 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
841 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
842 $setup(D, negedge C, 470 - 449);
843 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
844 $setup(R, negedge C, 203);
845 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
846 if ( R) (negedge C => (Q : 1'b0)) = 540;
847 if (!R) (negedge C => (Q : D)) = 540;
848 endspecify
849 `endif
850 `ifdef ICE40_LP
851 specify
852 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
853 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
854 $setup(D, negedge C, 693 - 662);
855 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
856 $setup(R, negedge C, 299);
857 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
858 if ( R) (negedge C => (Q : 1'b0)) = 796;
859 if (!R) (negedge C => (Q : D)) = 796;
860 endspecify
861 `endif
862 `ifdef ICE40_U
863 specify
864 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
865 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
866 $setup(D, negedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
867 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
868 $setup(R, negedge C, 530);
869 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
870 if ( R) (negedge C => (Q : 1'b0)) = 1391;
871 if (!R) (negedge C => (Q : D)) = 1391;
872 endspecify
873 `endif
874 endmodule
875
876 (* abc9_flop, lib_whitebox *)
877 module SB_DFFNR (
878 output `SB_DFF_REG,
879 input C, R, D
880 );
881 always @(negedge C, posedge R)
882 if (R)
883 Q <= 0;
884 else
885 Q <= D;
886 `ifdef ICE40_HX
887 specify
888 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
889 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
890 $setup(D, negedge C, 470 - 449);
891 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
892 $setup(negedge R, negedge C, 160);
893 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
894 (posedge R => (Q : 1'b0)) = 599;
895 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
896 if (!R) (negedge C => (Q : D)) = 540;
897 endspecify
898 `endif
899 `ifdef ICE40_LP
900 specify
901 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
902 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
903 $setup(D, negedge C, 693 - 662);
904 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
905 $setup(negedge R, negedge C, 235);
906 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
907 (posedge R => (Q : 1'b0)) = 883;
908 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
909 if (!R) (negedge C => (Q : D)) = 796;
910 endspecify
911 `endif
912 `ifdef ICE40_U
913 specify
914 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
915 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
916 $setup(D, negedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
917 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
918 $setup(negedge R, negedge C, 424);
919 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
920 (posedge R => (Q : 1'b0)) = 1589;
921 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
922 if (!R) (negedge C => (Q : D)) = 1391;
923 endspecify
924 `endif
925 endmodule
926
927 (* abc9_flop, lib_whitebox *)
928 module SB_DFFNSS (
929 output `SB_DFF_REG,
930 input C, S, D
931 );
932 always @(negedge C)
933 if (S)
934 Q <= 1;
935 else
936 Q <= D;
937 `ifdef ICE40_HX
938 specify
939 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
940 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
941 $setup(D, negedge C, 470 - 449);
942 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
943 $setup(S, negedge C, 203);
944 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
945 if ( S) (negedge C => (Q : 1'b1)) = 540;
946 if (!S) (negedge C => (Q : D)) = 540;
947 endspecify
948 `endif
949 `ifdef ICE40_LP
950 specify
951 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
952 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
953 $setup(D, negedge C, 693 - 662);
954 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
955 $setup(S, negedge C, 299);
956 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
957 if ( S) (negedge C => (Q : 1'b1)) = 796;
958 if (!S) (negedge C => (Q : D)) = 796;
959 endspecify
960 `endif
961 `ifdef ICE40_U
962 specify
963 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
964 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
965 $setup(D, negedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
966 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
967 $setup(S, negedge C, 530);
968 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
969 if ( S) (negedge C => (Q : 1'b1)) = 1391;
970 if (!S) (negedge C => (Q : D)) = 1391;
971 endspecify
972 `endif
973 endmodule
974
975 module SB_DFFNS (
976 output `SB_DFF_REG,
977 input C, S, D
978 );
979 always @(negedge C, posedge S)
980 if (S)
981 Q <= 1;
982 else
983 Q <= D;
984 `ifdef ICE40_HX
985 specify
986 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
987 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
988 $setup(D, negedge C, 470 - 449);
989 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
990 $setup(negedge S, negedge C, 160);
991 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
992 (posedge S => (Q : 1'b1)) = 599;
993 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
994 if (!S) (negedge C => (Q : D)) = 540;
995 endspecify
996 `endif
997 `ifdef ICE40_LP
998 specify
999 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
1000 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1001 $setup(D, negedge C, 693 - 662);
1002 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
1003 $setup(negedge S, negedge C, 235);
1004 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
1005 (posedge S => (Q : 1'b1)) = 883;
1006 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
1007 if (!S) (negedge C => (Q : D)) = 796;
1008 endspecify
1009 `endif
1010 `ifdef ICE40_U
1011 specify
1012 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
1013 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1014 $setup(D, negedge C, /*1232 - 1285*/ 0); // Negative times not currently supported
1015 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
1016 $setup(negedge S, negedge C, 424);
1017 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
1018 (posedge S => (Q : 1'b1)) = 1589;
1019 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
1020 if (!S) (negedge C => (Q : D)) = 1391;
1021 endspecify
1022 `endif
1023 endmodule
1024
1025 (* abc9_flop, lib_whitebox *)
1026 module SB_DFFNESR (
1027 output `SB_DFF_REG,
1028 input C, E, R, D
1029 );
1030 always @(negedge C)
1031 if (E) begin
1032 if (R)
1033 Q <= 0;
1034 else
1035 Q <= D;
1036 end
1037 `ifdef ICE40_HX
1038 specify
1039 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
1040 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
1041 $setup(D, negedge C &&& E && !R, 470 - 449);
1042 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
1043 $setup(E, negedge C, 0);
1044 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
1045 $setup(R, negedge C &&& E, 203);
1046 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
1047 if (E && R) (negedge C => (Q : 1'b0)) = 540;
1048 if (E && !R) (negedge C => (Q : D)) = 540;
1049 endspecify
1050 `endif
1051 `ifdef ICE40_LP
1052 specify
1053 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
1054 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1055 $setup(D, negedge C &&& E && !R, 693 - 662);
1056 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
1057 $setup(E, negedge C, 0);
1058 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
1059 $setup(R, negedge C &&& E, 299);
1060 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
1061 if (E && R) (negedge C => (Q : 1'b0)) = 796;
1062 if (E && !R) (negedge C => (Q : D)) = 796;
1063 endspecify
1064 `endif
1065 `ifdef ICE40_U
1066 specify
1067 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
1068 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1069 $setup(D, negedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
1070 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
1071 $setup(E, negedge C, 0);
1072 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
1073 $setup(R, negedge C &&& E, 530);
1074 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
1075 if (E && R) (negedge C => (Q : 1'b0)) = 1391;
1076 if (E && !R) (negedge C => (Q : D)) = 1391;
1077 endspecify
1078 `endif
1079 endmodule
1080
1081 module SB_DFFNER (
1082 output `SB_DFF_REG,
1083 input C, E, R, D
1084 );
1085 always @(negedge C, posedge R)
1086 if (R)
1087 Q <= 0;
1088 else if (E)
1089 Q <= D;
1090 `ifdef ICE40_HX
1091 specify
1092 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
1093 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
1094 $setup(D, negedge C &&& E, 470 - 449);
1095 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
1096 $setup(E, negedge C, 0);
1097 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
1098 $setup(R, negedge C, 2160);
1099 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
1100 (posedge R => (Q : 1'b0)) = 599;
1101 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
1102 if (E && !R) (negedge C => (Q : D)) = 540;
1103 endspecify
1104 `endif
1105 `ifdef ICE40_LP
1106 specify
1107 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
1108 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1109 $setup(D, negedge C &&& E, 693 - 662);
1110 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
1111 $setup(E, negedge C, 0);
1112 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
1113 $setup(R, negedge C, 235);
1114 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
1115 (posedge R => (Q : 1'b0)) = 883;
1116 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
1117 if (E && !R) (negedge C => (Q : D)) = 796;
1118 endspecify
1119 `endif
1120 `ifdef ICE40_U
1121 specify
1122 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
1123 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1124 $setup(D, negedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
1125 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
1126 $setup(E, negedge C, 0);
1127 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
1128 $setup(negedge R, negedge C, 424);
1129 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
1130 (posedge R => (Q : 1'b0)) = 1589;
1131 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
1132 if (E && !R) (negedge C => (Q : D)) = 1391;
1133 endspecify
1134 `endif
1135 endmodule
1136
1137 (* abc9_flop, lib_whitebox *)
1138 module SB_DFFNESS (
1139 output `SB_DFF_REG,
1140 input C, E, S, D
1141 );
1142 always @(negedge C)
1143 if (E) begin
1144 if (S)
1145 Q <= 1;
1146 else
1147 Q <= D;
1148 end
1149 `ifdef ICE40_HX
1150 specify
1151 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
1152 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
1153 $setup(D, negedge C &&& E && !S, 470 - 449);
1154 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
1155 $setup(E, negedge C, 0);
1156 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
1157 $setup(S, negedge C &&& E, 203);
1158 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
1159 if (E && S) (negedge C => (Q : 1'b1)) = 540;
1160 if (E && !S) (negedge C => (Q : D)) = 540;
1161 endspecify
1162 `endif
1163 `ifdef ICE40_LP
1164 specify
1165 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
1166 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1167 $setup(D, negedge C &&& E && !S, 693 - 662);
1168 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
1169 $setup(E, negedge C, 0);
1170 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
1171 $setup(S, negedge C &&& E, 299);
1172 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
1173 if (E && S) (negedge C => (Q : 1'b1)) = 796;
1174 if (E && !S) (negedge C => (Q : D)) = 796;
1175 endspecify
1176 `endif
1177 `ifdef ICE40_U
1178 specify
1179 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
1180 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1181 $setup(D, negedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
1182 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
1183 $setup(E, negedge C, 0);
1184 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
1185 $setup(S, negedge C &&& E, 530);
1186 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
1187 if (E && S) (negedge C => (Q : 1'b1)) = 1391;
1188 if (E && !S) (negedge C => (Q : D)) = 1391;
1189 endspecify
1190 `endif
1191 endmodule
1192
1193 module SB_DFFNES (
1194 output `SB_DFF_REG,
1195 input C, E, S, D
1196 );
1197 always @(negedge C, posedge S)
1198 if (S)
1199 Q <= 1;
1200 else if (E)
1201 Q <= D;
1202 `ifdef ICE40_HX
1203 specify
1204 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
1205 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
1206 $setup(D, negedge C &&& E, 470 - 449);
1207 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
1208 $setup(E, negedge C, 0);
1209 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
1210 $setup(negedge S, negedge C, 160);
1211 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
1212 (posedge S => (Q : 1'b1)) = 599;
1213 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
1214 if (E && !S) (negedge C => (Q : D)) = 540;
1215 endspecify
1216 `endif
1217 `ifdef ICE40_LP
1218 specify
1219 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
1220 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1221 $setup(D, negedge C &&& E, 693 - 662);
1222 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
1223 $setup(E, negedge C, 0);
1224 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
1225 $setup(negedge S, negedge C, 235);
1226 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
1227 (posedge S => (Q : 1'b1)) = 883;
1228 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
1229 if (E && !S) (negedge C => (Q : D)) = 796;
1230 endspecify
1231 `endif
1232 `ifdef ICE40_U
1233 specify
1234 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
1235 // minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
1236 $setup(D, negedge C &&& E, /*1232 - 1285*/ 0); // Negative times not currently supported
1237 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
1238 $setup(E, negedge C, 0);
1239 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
1240 $setup(negedge S, negedge C, 424);
1241 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
1242 (posedge S => (Q : 1'b1)) = 1589;
1243 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
1244 if (E && !S) (negedge C => (Q : D)) = 1391;
1245 endspecify
1246 `endif
1247 endmodule
1248
1249 // SiliconBlue RAM Cells
1250
1251 module SB_RAM40_4K (
1252 output [15:0] RDATA,
1253 input RCLK, RCLKE, RE,
1254 input [10:0] RADDR,
1255 input WCLK, WCLKE, WE,
1256 input [10:0] WADDR,
1257 input [15:0] MASK, WDATA
1258 );
1259 // MODE 0: 256 x 16
1260 // MODE 1: 512 x 8
1261 // MODE 2: 1024 x 4
1262 // MODE 3: 2048 x 2
1263 parameter WRITE_MODE = 0;
1264 parameter READ_MODE = 0;
1265
1266 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1267 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1268 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1269 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1270 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1271 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1272 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1273 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1274 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1275 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1276 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1277 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1278 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1279 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1280 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1281 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1282
1283 parameter INIT_FILE = "";
1284
1285 `ifndef BLACKBOX
1286 wire [15:0] WMASK_I;
1287 wire [15:0] RMASK_I;
1288
1289 reg [15:0] RDATA_I;
1290 wire [15:0] WDATA_I;
1291
1292 generate
1293 case (WRITE_MODE)
1294 0: assign WMASK_I = MASK;
1295
1296 1: assign WMASK_I = WADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
1297 WADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
1298
1299 2: assign WMASK_I = WADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
1300 WADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
1301 WADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
1302 WADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
1303
1304 3: assign WMASK_I = WADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
1305 WADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
1306 WADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
1307 WADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
1308 WADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
1309 WADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
1310 WADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
1311 WADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
1312 endcase
1313
1314 case (READ_MODE)
1315 0: assign RMASK_I = 16'b 0000_0000_0000_0000;
1316
1317 1: assign RMASK_I = RADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
1318 RADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
1319
1320 2: assign RMASK_I = RADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
1321 RADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
1322 RADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
1323 RADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
1324
1325 3: assign RMASK_I = RADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
1326 RADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
1327 RADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
1328 RADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
1329 RADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
1330 RADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
1331 RADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
1332 RADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
1333 endcase
1334
1335 case (WRITE_MODE)
1336 0: assign WDATA_I = WDATA;
1337
1338 1: assign WDATA_I = {WDATA[14], WDATA[14], WDATA[12], WDATA[12],
1339 WDATA[10], WDATA[10], WDATA[ 8], WDATA[ 8],
1340 WDATA[ 6], WDATA[ 6], WDATA[ 4], WDATA[ 4],
1341 WDATA[ 2], WDATA[ 2], WDATA[ 0], WDATA[ 0]};
1342
1343 2: assign WDATA_I = {WDATA[13], WDATA[13], WDATA[13], WDATA[13],
1344 WDATA[ 9], WDATA[ 9], WDATA[ 9], WDATA[ 9],
1345 WDATA[ 5], WDATA[ 5], WDATA[ 5], WDATA[ 5],
1346 WDATA[ 1], WDATA[ 1], WDATA[ 1], WDATA[ 1]};
1347
1348 3: assign WDATA_I = {WDATA[11], WDATA[11], WDATA[11], WDATA[11],
1349 WDATA[11], WDATA[11], WDATA[11], WDATA[11],
1350 WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3],
1351 WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3]};
1352 endcase
1353
1354 case (READ_MODE)
1355 0: assign RDATA = RDATA_I;
1356 1: assign RDATA = {1'b0, |RDATA_I[15:14], 1'b0, |RDATA_I[13:12], 1'b0, |RDATA_I[11:10], 1'b0, |RDATA_I[ 9: 8],
1357 1'b0, |RDATA_I[ 7: 6], 1'b0, |RDATA_I[ 5: 4], 1'b0, |RDATA_I[ 3: 2], 1'b0, |RDATA_I[ 1: 0]};
1358 2: assign RDATA = {2'b0, |RDATA_I[15:12], 3'b0, |RDATA_I[11: 8], 3'b0, |RDATA_I[ 7: 4], 3'b0, |RDATA_I[ 3: 0], 1'b0};
1359 3: assign RDATA = {4'b0, |RDATA_I[15: 8], 7'b0, |RDATA_I[ 7: 0], 3'b0};
1360 endcase
1361 endgenerate
1362
1363 integer i;
1364 reg [15:0] memory [0:255];
1365
1366 initial begin
1367 if (INIT_FILE != "")
1368 $readmemh(INIT_FILE, memory);
1369 else
1370 for (i=0; i<16; i=i+1) begin
1371 memory[ 0*16 + i] = INIT_0[16*i +: 16];
1372 memory[ 1*16 + i] = INIT_1[16*i +: 16];
1373 memory[ 2*16 + i] = INIT_2[16*i +: 16];
1374 memory[ 3*16 + i] = INIT_3[16*i +: 16];
1375 memory[ 4*16 + i] = INIT_4[16*i +: 16];
1376 memory[ 5*16 + i] = INIT_5[16*i +: 16];
1377 memory[ 6*16 + i] = INIT_6[16*i +: 16];
1378 memory[ 7*16 + i] = INIT_7[16*i +: 16];
1379 memory[ 8*16 + i] = INIT_8[16*i +: 16];
1380 memory[ 9*16 + i] = INIT_9[16*i +: 16];
1381 memory[10*16 + i] = INIT_A[16*i +: 16];
1382 memory[11*16 + i] = INIT_B[16*i +: 16];
1383 memory[12*16 + i] = INIT_C[16*i +: 16];
1384 memory[13*16 + i] = INIT_D[16*i +: 16];
1385 memory[14*16 + i] = INIT_E[16*i +: 16];
1386 memory[15*16 + i] = INIT_F[16*i +: 16];
1387 end
1388 end
1389
1390 always @(posedge WCLK) begin
1391 if (WE && WCLKE) begin
1392 if (!WMASK_I[ 0]) memory[WADDR[7:0]][ 0] <= WDATA_I[ 0];
1393 if (!WMASK_I[ 1]) memory[WADDR[7:0]][ 1] <= WDATA_I[ 1];
1394 if (!WMASK_I[ 2]) memory[WADDR[7:0]][ 2] <= WDATA_I[ 2];
1395 if (!WMASK_I[ 3]) memory[WADDR[7:0]][ 3] <= WDATA_I[ 3];
1396 if (!WMASK_I[ 4]) memory[WADDR[7:0]][ 4] <= WDATA_I[ 4];
1397 if (!WMASK_I[ 5]) memory[WADDR[7:0]][ 5] <= WDATA_I[ 5];
1398 if (!WMASK_I[ 6]) memory[WADDR[7:0]][ 6] <= WDATA_I[ 6];
1399 if (!WMASK_I[ 7]) memory[WADDR[7:0]][ 7] <= WDATA_I[ 7];
1400 if (!WMASK_I[ 8]) memory[WADDR[7:0]][ 8] <= WDATA_I[ 8];
1401 if (!WMASK_I[ 9]) memory[WADDR[7:0]][ 9] <= WDATA_I[ 9];
1402 if (!WMASK_I[10]) memory[WADDR[7:0]][10] <= WDATA_I[10];
1403 if (!WMASK_I[11]) memory[WADDR[7:0]][11] <= WDATA_I[11];
1404 if (!WMASK_I[12]) memory[WADDR[7:0]][12] <= WDATA_I[12];
1405 if (!WMASK_I[13]) memory[WADDR[7:0]][13] <= WDATA_I[13];
1406 if (!WMASK_I[14]) memory[WADDR[7:0]][14] <= WDATA_I[14];
1407 if (!WMASK_I[15]) memory[WADDR[7:0]][15] <= WDATA_I[15];
1408 end
1409 end
1410
1411 always @(posedge RCLK) begin
1412 if (RE && RCLKE) begin
1413 RDATA_I <= memory[RADDR[7:0]] & ~RMASK_I;
1414 end
1415 end
1416 `endif
1417 `ifdef ICE40_HX
1418 specify
1419 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L343-L358
1420 $setup(MASK, posedge WCLK &&& WE && WCLKE, 274);
1421 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L359-L369
1422 $setup(RADDR, posedge RCLK &&& RE && RCLKE, 203);
1423 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L370
1424 $setup(RCLKE, posedge RCLK, 267);
1425 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L371
1426 $setup(RE, posedge RCLK, 98);
1427 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L372-L382
1428 $setup(WADDR, posedge WCLK &&& WE && WCLKE, 224);
1429 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L383
1430 $setup(WCLKE, posedge WCLK, 267);
1431 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L384-L399
1432 $setup(WDATA, posedge WCLK &&& WE && WCLKE, 161);
1433 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
1434 $setup(WE, posedge WCLK, 133);
1435 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
1436 (posedge RCLK => (RDATA : 16'bx)) = 2146;
1437 endspecify
1438 `endif
1439 `ifdef ICE40_LP
1440 specify
1441 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L343-L358
1442 $setup(MASK, posedge WCLK &&& WE && WCLKE, 403);
1443 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L359-L369
1444 $setup(RADDR, posedge RCLK &&& RE && RCLKE, 300);
1445 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L370
1446 $setup(RCLKE, posedge RCLK, 393);
1447 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L371
1448 $setup(RE, posedge RCLK, 145);
1449 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L372-L382
1450 $setup(WADDR, posedge WCLK &&& WE && WCLKE, 331);
1451 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L383
1452 $setup(WCLKE, posedge WCLK, 393);
1453 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L384-L399
1454 $setup(WDATA, posedge WCLK &&& WE && WCLKE, 238);
1455 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
1456 $setup(WE, posedge WCLK, 196);
1457 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
1458 (posedge RCLK => (RDATA : 16'bx)) = 3163;
1459 endspecify
1460 `endif
1461 `ifdef ICE40_U
1462 specify
1463 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12968-12983
1464 $setup(MASK, posedge WCLK &&& WE && WCLKE, 517);
1465 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12984-12994
1466 $setup(RADDR, posedge RCLK &&& RE && RCLKE, 384);
1467 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12995
1468 $setup(RCLKE, posedge RCLK, 503);
1469 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12996
1470 $setup(RE, posedge RCLK, 185);
1471 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12997-13007
1472 $setup(WADDR, posedge WCLK &&& WE && WCLKE, 424);
1473 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13008
1474 $setup(WCLKE, posedge WCLK, 503);
1475 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13009-13024
1476 $setup(WDATA, posedge WCLK &&& WE && WCLKE, 305);
1477 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
1478 $setup(WE, posedge WCLK, 252);
1479 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
1480 (posedge RCLK => (RDATA : 16'bx)) = 1179;
1481 endspecify
1482 `endif
1483 endmodule
1484
1485 module SB_RAM40_4KNR (
1486 output [15:0] RDATA,
1487 input RCLKN, RCLKE, RE,
1488 input [10:0] RADDR,
1489 input WCLK, WCLKE, WE,
1490 input [10:0] WADDR,
1491 input [15:0] MASK, WDATA
1492 );
1493 parameter WRITE_MODE = 0;
1494 parameter READ_MODE = 0;
1495
1496 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1497 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1498 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1499 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1500 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1501 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1502 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1503 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1504 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1505 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1506 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1507 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1508 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1509 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1510 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1511 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1512
1513 parameter INIT_FILE = "";
1514
1515 SB_RAM40_4K #(
1516 .WRITE_MODE(WRITE_MODE),
1517 .READ_MODE (READ_MODE ),
1518 .INIT_0 (INIT_0 ),
1519 .INIT_1 (INIT_1 ),
1520 .INIT_2 (INIT_2 ),
1521 .INIT_3 (INIT_3 ),
1522 .INIT_4 (INIT_4 ),
1523 .INIT_5 (INIT_5 ),
1524 .INIT_6 (INIT_6 ),
1525 .INIT_7 (INIT_7 ),
1526 .INIT_8 (INIT_8 ),
1527 .INIT_9 (INIT_9 ),
1528 .INIT_A (INIT_A ),
1529 .INIT_B (INIT_B ),
1530 .INIT_C (INIT_C ),
1531 .INIT_D (INIT_D ),
1532 .INIT_E (INIT_E ),
1533 .INIT_F (INIT_F ),
1534 .INIT_FILE (INIT_FILE )
1535 ) RAM (
1536 .RDATA(RDATA),
1537 .RCLK (~RCLKN),
1538 .RCLKE(RCLKE),
1539 .RE (RE ),
1540 .RADDR(RADDR),
1541 .WCLK (WCLK ),
1542 .WCLKE(WCLKE),
1543 .WE (WE ),
1544 .WADDR(WADDR),
1545 .MASK (MASK ),
1546 .WDATA(WDATA)
1547 );
1548 `ifdef ICE40_HX
1549 specify
1550 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L343-L358
1551 $setup(MASK, posedge WCLK &&& WE && WCLKE, 274);
1552 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L359-L369
1553 $setup(RADDR, posedge RCLKN &&& RE && RCLKE, 203);
1554 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L370
1555 $setup(RCLKE, posedge RCLKN, 267);
1556 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L371
1557 $setup(RE, posedge RCLKN, 98);
1558 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L372-L382
1559 $setup(WADDR, posedge WCLK &&& WE && WCLKE, 224);
1560 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L383
1561 $setup(WCLKE, posedge WCLK, 267);
1562 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L384-L399
1563 $setup(WDATA, posedge WCLK &&& WE && WCLKE, 161);
1564 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
1565 $setup(WE, posedge WCLK, 133);
1566 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
1567 (posedge RCLKN => (RDATA : 16'bx)) = 2146;
1568 endspecify
1569 `endif
1570 `ifdef ICE40_LP
1571 specify
1572 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L343-L358
1573 $setup(MASK, posedge WCLK &&& WE && WCLKE, 403);
1574 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L359-L369
1575 $setup(RADDR, posedge RCLKN &&& RE && RCLKE, 300);
1576 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L370
1577 $setup(RCLKE, posedge RCLKN, 393);
1578 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L371
1579 $setup(RE, posedge RCLKN, 145);
1580 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L372-L382
1581 $setup(WADDR, posedge WCLK &&& WE && WCLKE, 331);
1582 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L383
1583 $setup(WCLKE, posedge WCLK, 393);
1584 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L384-L399
1585 $setup(WDATA, posedge WCLK &&& WE && WCLKE, 238);
1586 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
1587 $setup(WE, posedge WCLK, 196);
1588 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
1589 (posedge RCLKN => (RDATA : 16'bx)) = 3163;
1590 endspecify
1591 `endif
1592 `ifdef ICE40_U
1593 specify
1594 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12968-12983
1595 $setup(MASK, posedge WCLK &&& WE && WCLKE, 517);
1596 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12984-12994
1597 $setup(RADDR, posedge RCLKN &&& RE && RCLKE, 384);
1598 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12995
1599 $setup(RCLKE, posedge RCLKN, 503);
1600 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12996
1601 $setup(RE, posedge RCLKN, 185);
1602 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12997-13007
1603 $setup(WADDR, posedge WCLK &&& WE && WCLKE, 424);
1604 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13008
1605 $setup(WCLKE, posedge WCLK, 503);
1606 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13009-13024
1607 $setup(WDATA, posedge WCLK &&& WE && WCLKE, 305);
1608 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
1609 $setup(WE, posedge WCLK, 252);
1610 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
1611 (posedge RCLKN => (RDATA : 16'bx)) = 1179;
1612 endspecify
1613 `endif
1614 endmodule
1615
1616 module SB_RAM40_4KNW (
1617 output [15:0] RDATA,
1618 input RCLK, RCLKE, RE,
1619 input [10:0] RADDR,
1620 input WCLKN, WCLKE, WE,
1621 input [10:0] WADDR,
1622 input [15:0] MASK, WDATA
1623 );
1624 parameter WRITE_MODE = 0;
1625 parameter READ_MODE = 0;
1626
1627 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1628 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1629 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1630 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1631 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1632 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1633 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1634 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1635 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1636 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1637 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1638 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1639 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1640 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1641 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1642 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1643
1644 parameter INIT_FILE = "";
1645
1646 SB_RAM40_4K #(
1647 .WRITE_MODE(WRITE_MODE),
1648 .READ_MODE (READ_MODE ),
1649 .INIT_0 (INIT_0 ),
1650 .INIT_1 (INIT_1 ),
1651 .INIT_2 (INIT_2 ),
1652 .INIT_3 (INIT_3 ),
1653 .INIT_4 (INIT_4 ),
1654 .INIT_5 (INIT_5 ),
1655 .INIT_6 (INIT_6 ),
1656 .INIT_7 (INIT_7 ),
1657 .INIT_8 (INIT_8 ),
1658 .INIT_9 (INIT_9 ),
1659 .INIT_A (INIT_A ),
1660 .INIT_B (INIT_B ),
1661 .INIT_C (INIT_C ),
1662 .INIT_D (INIT_D ),
1663 .INIT_E (INIT_E ),
1664 .INIT_F (INIT_F ),
1665 .INIT_FILE (INIT_FILE )
1666 ) RAM (
1667 .RDATA(RDATA),
1668 .RCLK (RCLK ),
1669 .RCLKE(RCLKE),
1670 .RE (RE ),
1671 .RADDR(RADDR),
1672 .WCLK (~WCLKN),
1673 .WCLKE(WCLKE),
1674 .WE (WE ),
1675 .WADDR(WADDR),
1676 .MASK (MASK ),
1677 .WDATA(WDATA)
1678 );
1679 `ifdef ICE40_HX
1680 specify
1681 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L343-L358
1682 $setup(MASK, posedge WCLKN &&& WE && WCLKE, 274);
1683 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L359-L369
1684 $setup(RADDR, posedge RCLK &&& RE && RCLKE, 203);
1685 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L370
1686 $setup(RCLKE, posedge RCLK, 267);
1687 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L371
1688 $setup(RE, posedge RCLK, 98);
1689 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L372-L382
1690 $setup(WADDR, posedge WCLKN &&& WE && WCLKE, 224);
1691 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L383
1692 $setup(WCLKE, posedge WCLKN, 267);
1693 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L384-L399
1694 $setup(WDATA, posedge WCLKN &&& WE && WCLKE, 161);
1695 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
1696 $setup(WE, posedge WCLKN, 133);
1697 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
1698 (posedge RCLK => (RDATA : 16'bx)) = 2146;
1699 endspecify
1700 `endif
1701 `ifdef ICE40_LP
1702 specify
1703 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L343-L358
1704 $setup(MASK, posedge WCLKN &&& WE && WCLKE, 403);
1705 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L359-L369
1706 $setup(RADDR, posedge RCLK &&& RE && RCLKE, 300);
1707 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L370
1708 $setup(RCLKE, posedge RCLK, 393);
1709 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L371
1710 $setup(RE, posedge RCLK, 145);
1711 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L372-L382
1712 $setup(WADDR, posedge WCLKN &&& WE && WCLKE, 331);
1713 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L383
1714 $setup(WCLKE, posedge WCLKN, 393);
1715 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L384-L399
1716 $setup(WDATA, posedge WCLKN &&& WE && WCLKE, 238);
1717 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
1718 $setup(WE, posedge WCLKN, 196);
1719 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
1720 (posedge RCLK => (RDATA : 16'bx)) = 3163;
1721 endspecify
1722 `endif
1723 `ifdef ICE40_U
1724 specify
1725 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12968-12983
1726 $setup(MASK, posedge WCLKN &&& WE && WCLKE, 517);
1727 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12984-12994
1728 $setup(RADDR, posedge RCLK &&& RE && RCLKE, 384);
1729 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12995
1730 $setup(RCLKE, posedge RCLK, 503);
1731 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12996
1732 $setup(RE, posedge RCLK, 185);
1733 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12997-13007
1734 $setup(WADDR, posedge WCLKN &&& WE && WCLKE, 424);
1735 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13008
1736 $setup(WCLKE, posedge WCLKN, 503);
1737 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13009-13024
1738 $setup(WDATA, posedge WCLKN &&& WE && WCLKE, 305);
1739 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
1740 $setup(WE, posedge WCLKN, 252);
1741 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
1742 (posedge RCLK => (RDATA : 16'bx)) = 1179;
1743 endspecify
1744 `endif
1745 endmodule
1746
1747 module SB_RAM40_4KNRNW (
1748 output [15:0] RDATA,
1749 input RCLKN, RCLKE, RE,
1750 input [10:0] RADDR,
1751 input WCLKN, WCLKE, WE,
1752 input [10:0] WADDR,
1753 input [15:0] MASK, WDATA
1754 );
1755 parameter WRITE_MODE = 0;
1756 parameter READ_MODE = 0;
1757
1758 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1759 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1760 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1761 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1762 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1763 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1764 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1765 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1766 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1767 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1768 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1769 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1770 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1771 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1772 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1773 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1774
1775 parameter INIT_FILE = "";
1776
1777 SB_RAM40_4K #(
1778 .WRITE_MODE(WRITE_MODE),
1779 .READ_MODE (READ_MODE ),
1780 .INIT_0 (INIT_0 ),
1781 .INIT_1 (INIT_1 ),
1782 .INIT_2 (INIT_2 ),
1783 .INIT_3 (INIT_3 ),
1784 .INIT_4 (INIT_4 ),
1785 .INIT_5 (INIT_5 ),
1786 .INIT_6 (INIT_6 ),
1787 .INIT_7 (INIT_7 ),
1788 .INIT_8 (INIT_8 ),
1789 .INIT_9 (INIT_9 ),
1790 .INIT_A (INIT_A ),
1791 .INIT_B (INIT_B ),
1792 .INIT_C (INIT_C ),
1793 .INIT_D (INIT_D ),
1794 .INIT_E (INIT_E ),
1795 .INIT_F (INIT_F ),
1796 .INIT_FILE (INIT_FILE )
1797 ) RAM (
1798 .RDATA(RDATA),
1799 .RCLK (~RCLKN),
1800 .RCLKE(RCLKE),
1801 .RE (RE ),
1802 .RADDR(RADDR),
1803 .WCLK (~WCLKN),
1804 .WCLKE(WCLKE),
1805 .WE (WE ),
1806 .WADDR(WADDR),
1807 .MASK (MASK ),
1808 .WDATA(WDATA)
1809 );
1810 `ifdef ICE40_HX
1811 specify
1812 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L343-L358
1813 $setup(MASK, posedge WCLKN &&& WE && WCLKE, 274);
1814 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L359-L369
1815 $setup(RADDR, posedge RCLKN &&& RE && RCLKE, 203);
1816 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L370
1817 $setup(RCLKE, posedge RCLKN, 267);
1818 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L371
1819 $setup(RE, posedge RCLKN, 98);
1820 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L372-L382
1821 $setup(WADDR, posedge WCLKN &&& WE && WCLKE, 224);
1822 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L383
1823 $setup(WCLKE, posedge WCLKN, 267);
1824 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L384-L399
1825 $setup(WDATA, posedge WCLKN &&& WE && WCLKE, 161);
1826 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
1827 $setup(WE, posedge WCLKN, 133);
1828 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
1829 (posedge RCLKN => (RDATA : 16'bx)) = 2146;
1830 endspecify
1831 `endif
1832 `ifdef ICE40_LP
1833 specify
1834 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L343-L358
1835 $setup(MASK, posedge WCLKN &&& WE && WCLKE, 403);
1836 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L359-L369
1837 $setup(RADDR, posedge RCLKN &&& RE && RCLKE, 300);
1838 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L370
1839 $setup(RCLKE, posedge RCLKN, 393);
1840 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L371
1841 $setup(RE, posedge RCLKN, 145);
1842 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L372-L382
1843 $setup(WADDR, posedge WCLKN &&& WE && WCLKE, 331);
1844 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L383
1845 $setup(WCLKE, posedge WCLKN, 393);
1846 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L384-L399
1847 $setup(WDATA, posedge WCLKN &&& WE && WCLKE, 238);
1848 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
1849 $setup(WE, posedge WCLKN, 196);
1850 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
1851 (posedge RCLKN => (RDATA : 16'bx)) = 3163;
1852 endspecify
1853 `endif
1854 `ifdef ICE40_U
1855 specify
1856 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12968-12983
1857 $setup(MASK, posedge WCLKN &&& WE && WCLKE, 517);
1858 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12984-12994
1859 $setup(RADDR, posedge RCLKN &&& RE && RCLKE, 384);
1860 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12995
1861 $setup(RCLKE, posedge RCLKN, 503);
1862 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12996
1863 $setup(RE, posedge RCLKN, 185);
1864 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12997-13007
1865 $setup(WADDR, posedge WCLKN &&& WE && WCLKE, 424);
1866 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13008
1867 $setup(WCLKE, posedge WCLKN, 503);
1868 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13009-13024
1869 $setup(WDATA, posedge WCLKN &&& WE && WCLKE, 305);
1870 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
1871 $setup(WE, posedge WCLKN, 252);
1872 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
1873 (posedge RCLKN => (RDATA : 16'bx)) = 1179;
1874 endspecify
1875 `endif
1876 endmodule
1877
1878 // Packed IceStorm Logic Cells
1879
1880 module ICESTORM_LC (
1881 input I0, I1, I2, I3, CIN, CLK, CEN, SR,
1882 output LO,
1883 output O,
1884 output COUT
1885 );
1886 parameter [15:0] LUT_INIT = 0;
1887
1888 parameter [0:0] NEG_CLK = 0;
1889 parameter [0:0] CARRY_ENABLE = 0;
1890 parameter [0:0] DFF_ENABLE = 0;
1891 parameter [0:0] SET_NORESET = 0;
1892 parameter [0:0] ASYNC_SR = 0;
1893
1894 parameter [0:0] CIN_CONST = 0;
1895 parameter [0:0] CIN_SET = 0;
1896
1897 wire I0_pd = (I0 === 1'bz) ? 1'b0 : I0;
1898 wire I1_pd = (I1 === 1'bz) ? 1'b0 : I1;
1899 wire I2_pd = (I2 === 1'bz) ? 1'b0 : I2;
1900 wire I3_pd = (I3 === 1'bz) ? 1'b0 : I3;
1901 wire SR_pd = (SR === 1'bz) ? 1'b0 : SR;
1902 wire CEN_pu = (CEN === 1'bz) ? 1'b1 : CEN;
1903
1904 wire mux_cin = CIN_CONST ? CIN_SET : CIN;
1905
1906 assign COUT = CARRY_ENABLE ? (I1_pd && I2_pd) || ((I1_pd || I2_pd) && mux_cin) : 1'bx;
1907
1908 wire [7:0] lut_s3 = I3_pd ? LUT_INIT[15:8] : LUT_INIT[7:0];
1909 wire [3:0] lut_s2 = I2_pd ? lut_s3[ 7:4] : lut_s3[3:0];
1910 wire [1:0] lut_s1 = I1_pd ? lut_s2[ 3:2] : lut_s2[1:0];
1911 wire lut_o = I0_pd ? lut_s1[ 1] : lut_s1[ 0];
1912
1913 assign LO = lut_o;
1914
1915 wire polarized_clk;
1916 assign polarized_clk = CLK ^ NEG_CLK;
1917
1918 reg o_reg = 1'b0;
1919 always @(posedge polarized_clk)
1920 if (CEN_pu)
1921 o_reg <= SR_pd ? SET_NORESET : lut_o;
1922
1923 reg o_reg_async = 1'b0;
1924 always @(posedge polarized_clk, posedge SR_pd)
1925 if (SR_pd)
1926 o_reg_async <= SET_NORESET;
1927 else if (CEN_pu)
1928 o_reg_async <= lut_o;
1929
1930 assign O = DFF_ENABLE ? ASYNC_SR ? o_reg_async : o_reg : lut_o;
1931 `ifdef TIMING
1932 specify
1933 (I0 => O) = (0:0:0, 0:0:0);
1934 (I1 => O) = (0:0:0, 0:0:0);
1935 (I2 => O) = (0:0:0, 0:0:0);
1936 (I3 => O) = (0:0:0, 0:0:0);
1937 (I0 => LO) = (0:0:0, 0:0:0);
1938 (I1 => LO) = (0:0:0, 0:0:0);
1939 (I2 => LO) = (0:0:0, 0:0:0);
1940 (I3 => LO) = (0:0:0, 0:0:0);
1941 (I1 => COUT) = (0:0:0, 0:0:0);
1942 (I2 => COUT) = (0:0:0, 0:0:0);
1943 (CIN => COUT) = (0:0:0, 0:0:0);
1944 (CLK => O) = (0:0:0, 0:0:0);
1945 (SR => O) = (0:0:0, 0:0:0);
1946 $setuphold(posedge CLK, posedge I0, 0:0:0, 0:0:0);
1947 $setuphold(posedge CLK, negedge I0, 0:0:0, 0:0:0);
1948 $setuphold(negedge CLK, posedge I0, 0:0:0, 0:0:0);
1949 $setuphold(negedge CLK, negedge I0, 0:0:0, 0:0:0);
1950 $setuphold(posedge CLK, posedge I1, 0:0:0, 0:0:0);
1951 $setuphold(posedge CLK, negedge I1, 0:0:0, 0:0:0);
1952 $setuphold(negedge CLK, posedge I1, 0:0:0, 0:0:0);
1953 $setuphold(negedge CLK, negedge I1, 0:0:0, 0:0:0);
1954 $setuphold(posedge CLK, posedge I2, 0:0:0, 0:0:0);
1955 $setuphold(posedge CLK, negedge I2, 0:0:0, 0:0:0);
1956 $setuphold(negedge CLK, posedge I2, 0:0:0, 0:0:0);
1957 $setuphold(negedge CLK, negedge I2, 0:0:0, 0:0:0);
1958 $setuphold(posedge CLK, posedge I3, 0:0:0, 0:0:0);
1959 $setuphold(posedge CLK, negedge I3, 0:0:0, 0:0:0);
1960 $setuphold(negedge CLK, posedge I3, 0:0:0, 0:0:0);
1961 $setuphold(negedge CLK, negedge I3, 0:0:0, 0:0:0);
1962 $setuphold(posedge CLK, posedge CEN, 0:0:0, 0:0:0);
1963 $setuphold(posedge CLK, negedge CEN, 0:0:0, 0:0:0);
1964 $setuphold(negedge CLK, posedge CEN, 0:0:0, 0:0:0);
1965 $setuphold(negedge CLK, negedge CEN, 0:0:0, 0:0:0);
1966 $setuphold(posedge CLK, posedge SR, 0:0:0, 0:0:0);
1967 $setuphold(posedge CLK, negedge SR, 0:0:0, 0:0:0);
1968 $setuphold(negedge CLK, posedge SR, 0:0:0, 0:0:0);
1969 $setuphold(negedge CLK, negedge SR, 0:0:0, 0:0:0);
1970 endspecify
1971 `endif
1972 `ifdef ICE40_HX
1973 specify
1974 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L79
1975 (CIN => COUT) = (101:112:126, 85:94:105);
1976 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
1977 (I0 => O) = (361:399:449, 310:343:386);
1978 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L81
1979 (I0 => LO) = (293:324:365, 310:343:386);
1980 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L82
1981 (I1 => COUT) = (209:231:259, 197:218:245);
1982 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L83
1983 (I1 => O) = (321:355:400, 304:337:379);
1984 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L84
1985 (I1 => LO) = (259:287:323, 304:337:379);
1986 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L85
1987 (I2 => COUT) = (186:206:231, 107:118:133);
1988 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L86
1989 (I2 => O) = (304:337:379, 282:312:351);
1990 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L87
1991 (I2 => LO) = (254:281:316, 231:256:288);
1992 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L88
1993 (I3 => O) = (254:281:316, 231:256:288);
1994 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L89
1995 (I3 => LO) = (214:237:267, 220:243:274);
1996 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
1997 (posedge CLK => (O : 1'bx)) = (434:480:540, 434:480:540);
1998 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91-L92
1999 (SR => O) = (482:535:599, 482:533:599);
2000 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
2001 $setuphold(posedge CLK, posedge I0, 378:418:470, 0:0:0);
2002 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L68
2003 $setuphold(posedge CLK, negedge I0, 321:355:400, 0:0:0);
2004 $setuphold(negedge CLK, posedge I0, 378:418:470, 0:0:0);
2005 $setuphold(negedge CLK, negedge I0, 321:355:400, 0:0:0);
2006 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L75
2007 $setuphold(posedge CLK, posedge I1, 321:355:400, 0:0:0);
2008 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L69
2009 $setuphold(posedge CLK, negedge I1, 304:337:379, 0:0:0);
2010 $setuphold(negedge CLK, posedge I1, 321:355:400, 0:0:0);
2011 $setuphold(negedge CLK, negedge I1, 304:337:379, 0:0:0);
2012 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L76
2013 $setuphold(posedge CLK, posedge I2, 299:330:372, 0:0:0);
2014 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L70
2015 $setuphold(posedge CLK, negedge I2, 259:287:323, 0:0:0);
2016 $setuphold(negedge CLK, posedge I2, 299:330:372, 0:0:0);
2017 $setuphold(negedge CLK, negedge I2, 259:287:323, 0:0:0);
2018 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L77
2019 $setuphold(posedge CLK, posedge I3, 220:243:274, 0:0:0);
2020 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L71
2021 $setuphold(posedge CLK, negedge I3, 175:183:217, 0:0:0);
2022 $setuphold(negedge CLK, posedge I3, 220:243:274, 0:0:0);
2023 $setuphold(negedge CLK, negedge I3, 175:183:217, 0:0:0);
2024 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
2025 $setuphold(posedge CLK, negedge CEN, 0:0:0, 0:0:0);
2026 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L67
2027 $setuphold(posedge CLK, posedge CEN, 0:0:0, 0:0:0);
2028 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
2029 $setuphold(posedge CLK, posedge SR, 163:181:203, 0:0:0);
2030 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L72
2031 $setuphold(posedge CLK, negedge SR, 113:125:140, 0:0:0);
2032 $setuphold(negedge CLK, posedge SR, 163:181:203, 0:0:0);
2033 $setuphold(negedge CLK, negedge SR, 113:125:140, 0:0:0);
2034 endspecify
2035 `endif
2036 `ifdef ICE40_LP
2037 specify
2038 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L79
2039 (CIN => COUT) = (118:153:186, 98:128:155);
2040 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
2041 (I0 => O) = (419:545:662, 360:468:569);
2042 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L81
2043 (I0 => LO) = (340:442:538, 360:468:569);
2044 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L82
2045 (I1 => COUT) = (242:315:382, 229:298:362);
2046 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L83
2047 (I1 => O) = (372:485:589, 353:459:558);
2048 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L84
2049 (I1 => LO) = (301:391:475, 353:459:558);
2050 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L85
2051 (I2 => COUT) = (216:281:341, 124:162:196);
2052 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
2053 (I2 => O) = (353:459:558, 327:425:517);
2054 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L87
2055 (I2 => LO) = (288:374:455, 321:417:507);
2056 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L88
2057 (I3 => O) = (294:383:465, 268:349:424);
2058 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L89
2059 (I3 => LO) = (249:323:393, 255:332:403);
2060 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
2061 (posedge CLK => (O : 1'bx)) = (504:655:796, 504:655:796);
2062 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91-L92
2063 (SR => O) = (559:726:883, 559:726:883);
2064 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
2065 $setuphold(posedge CLK, posedge I0, 438:570:693, 0:0:0);
2066 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L68
2067 $setuphold(posedge CLK, negedge I0, 373:485:589, 0:0:0);
2068 $setuphold(negedge CLK, posedge I0, 438:570:693, 0:0:0);
2069 $setuphold(negedge CLK, negedge I0, 373:485:589, 0:0:0);
2070 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L75
2071 $setuphold(posedge CLK, posedge I1, 373:485:589, 0:0:0);
2072 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L69
2073 $setuphold(posedge CLK, negedge I1, 353:459:558, 0:0:0);
2074 $setuphold(negedge CLK, posedge I1, 373:485:589, 0:0:0);
2075 $setuphold(negedge CLK, negedge I1, 353:459:558, 0:0:0);
2076 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L76
2077 $setuphold(posedge CLK, posedge I2, 347:451:548, 0:0:0);
2078 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L70
2079 $setuphold(posedge CLK, negedge I2, 301:391:475, 0:0:0);
2080 $setuphold(negedge CLK, posedge I2, 347:451:548, 0:0:0);
2081 $setuphold(negedge CLK, negedge I2, 301:391:475, 0:0:0);
2082 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L77
2083 $setuphold(posedge CLK, posedge I3, 255:332:403, 0:0:0);
2084 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L71
2085 $setuphold(posedge CLK, negedge I3, 203:264:320, 0:0:0);
2086 $setuphold(negedge CLK, posedge I3, 255:332:403, 0:0:0);
2087 $setuphold(negedge CLK, negedge I3, 203:264:320, 0:0:0);
2088 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
2089 $setuphold(posedge CLK, negedge CEN, 0:0:0, 0:0:0);
2090 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L67
2091 $setuphold(posedge CLK, posedge CEN, 0:0:0, 0:0:0);
2092 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
2093 $setuphold(posedge CLK, posedge SR, 190:247:300, 0:0:0);
2094 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L72
2095 $setuphold(posedge CLK, negedge SR, 131:170:207, 0:0:0);
2096 $setuphold(negedge CLK, posedge SR, 190:247:300, 0:0:0);
2097 $setuphold(negedge CLK, negedge SR, 131:170:207, 0:0:0);
2098 endspecify
2099 `endif
2100 `ifdef ICE40_U
2101 specify
2102 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L91
2103 (CIN => COUT) = (103:181:278, 103:181:278);
2104 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L92
2105 (I0 => O) = (462:808:1255, 477:834:1285);
2106 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L93
2107 (I0 => LO) = (315:550:848, 334:585:901);
2108 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L94
2109 (I1 => COUT) = (251:438:675, 246:430:662);
2110 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L95
2111 (I1 => O) = (438:765:1179, 457:799:1232);
2112 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L96
2113 (I1 => LO) = (275:481:742, 329:576:887);
2114 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L97
2115 (I2 => COUT) = (226:395:609, 133:232:358);
2116 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L98
2117 (I2 => O) = (438:765:1179, 447:782:1205);
2118 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L99
2119 (I2 => LO) = (261:456:702, 290:507:781);
2120 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L100
2121 (I3 => O) = (320:559:861, 226:370:874);
2122 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L101
2123 (I3 => LO) = (216:378:583, 226:395:609);
2124 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
2125 (posedge CLK => (O : 1'bx)) = (516:903:1391, 516:903:1391);
2126 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103-104
2127 (SR => O) = (420:734:1131, 590:1032:1589);
2128 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
2129 $setuphold(posedge CLK, posedge I0, 457:799:1232, 0:0:0);
2130 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L80
2131 $setuphold(posedge CLK, negedge I0, 393:688:1060, 0:0:0);
2132 $setuphold(negedge CLK, posedge I0, 457:799:1232, 0:0:0);
2133 $setuphold(negedge CLK, negedge I0, 393:688:1060, 0:0:0);
2134 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L87
2135 $setuphold(posedge CLK, posedge I1, 393:688:1060, 0:0:0);
2136 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L81
2137 $setuphold(posedge CLK, negedge I1, 373:653:1007, 0:0:0);
2138 $setuphold(negedge CLK, posedge I1, 393:688:1060, 0:0:0);
2139 $setuphold(negedge CLK, negedge I1, 373:653:1007, 0:0:0);
2140 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L88
2141 $setuphold(posedge CLK, posedge I2, 364:636:980, 0:0:0);
2142 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L82
2143 $setuphold(posedge CLK, negedge I2, 320:559:861, 0:0:0);
2144 $setuphold(negedge CLK, posedge I2, 364:636:980, 0:0:0);
2145 $setuphold(negedge CLK, negedge I2, 320:559:861, 0:0:0);
2146 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L89
2147 $setuphold(posedge CLK, posedge I3, 279:473:728, 0:0:0);
2148 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L83
2149 $setuphold(posedge CLK, negedge I3, 216:378:583, 0:0:0);
2150 $setuphold(negedge CLK, posedge I3, 279:473:728, 0:0:0);
2151 $setuphold(negedge CLK, negedge I3, 216:378:583, 0:0:0);
2152 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L85
2153 $setuphold(posedge CLK, negedge CEN, 0:0:0, 0:0:0);
2154 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L79
2155 $setuphold(posedge CLK, posedge CEN, 0:0:0, 0:0:0);
2156 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
2157 $setuphold(posedge CLK, posedge SR, 197:344:530, 0:0:0);
2158 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L84
2159 $setuphold(posedge CLK, negedge SR, 143:249:384, 0:0:0);
2160 $setuphold(negedge CLK, posedge SR, 197:344:530, 0:0:0);
2161 $setuphold(negedge CLK, negedge SR, 131:170:207, 0:0:0);
2162 endspecify
2163 `endif
2164 endmodule
2165
2166 // SiliconBlue PLL Cells
2167
2168 (* blackbox *)
2169 module SB_PLL40_CORE (
2170 input REFERENCECLK,
2171 output PLLOUTCORE,
2172 output PLLOUTGLOBAL,
2173 input EXTFEEDBACK,
2174 input [7:0] DYNAMICDELAY,
2175 output LOCK,
2176 input BYPASS,
2177 input RESETB,
2178 input LATCHINPUTVALUE,
2179 output SDO,
2180 input SDI,
2181 input SCLK
2182 );
2183 parameter FEEDBACK_PATH = "SIMPLE";
2184 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
2185 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
2186 parameter SHIFTREG_DIV_MODE = 1'b0;
2187 parameter FDA_FEEDBACK = 4'b0000;
2188 parameter FDA_RELATIVE = 4'b0000;
2189 parameter PLLOUT_SELECT = "GENCLK";
2190 parameter DIVR = 4'b0000;
2191 parameter DIVF = 7'b0000000;
2192 parameter DIVQ = 3'b000;
2193 parameter FILTER_RANGE = 3'b000;
2194 parameter ENABLE_ICEGATE = 1'b0;
2195 parameter TEST_MODE = 1'b0;
2196 parameter EXTERNAL_DIVIDE_FACTOR = 1;
2197 endmodule
2198
2199 (* blackbox *)
2200 module SB_PLL40_PAD (
2201 input PACKAGEPIN,
2202 output PLLOUTCORE,
2203 output PLLOUTGLOBAL,
2204 input EXTFEEDBACK,
2205 input [7:0] DYNAMICDELAY,
2206 output LOCK,
2207 input BYPASS,
2208 input RESETB,
2209 input LATCHINPUTVALUE,
2210 output SDO,
2211 input SDI,
2212 input SCLK
2213 );
2214 parameter FEEDBACK_PATH = "SIMPLE";
2215 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
2216 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
2217 parameter SHIFTREG_DIV_MODE = 1'b0;
2218 parameter FDA_FEEDBACK = 4'b0000;
2219 parameter FDA_RELATIVE = 4'b0000;
2220 parameter PLLOUT_SELECT = "GENCLK";
2221 parameter DIVR = 4'b0000;
2222 parameter DIVF = 7'b0000000;
2223 parameter DIVQ = 3'b000;
2224 parameter FILTER_RANGE = 3'b000;
2225 parameter ENABLE_ICEGATE = 1'b0;
2226 parameter TEST_MODE = 1'b0;
2227 parameter EXTERNAL_DIVIDE_FACTOR = 1;
2228 endmodule
2229
2230 (* blackbox *)
2231 module SB_PLL40_2_PAD (
2232 input PACKAGEPIN,
2233 output PLLOUTCOREA,
2234 output PLLOUTGLOBALA,
2235 output PLLOUTCOREB,
2236 output PLLOUTGLOBALB,
2237 input EXTFEEDBACK,
2238 input [7:0] DYNAMICDELAY,
2239 output LOCK,
2240 input BYPASS,
2241 input RESETB,
2242 input LATCHINPUTVALUE,
2243 output SDO,
2244 input SDI,
2245 input SCLK
2246 );
2247 parameter FEEDBACK_PATH = "SIMPLE";
2248 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
2249 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
2250 parameter SHIFTREG_DIV_MODE = 1'b0;
2251 parameter FDA_FEEDBACK = 4'b0000;
2252 parameter FDA_RELATIVE = 4'b0000;
2253 parameter PLLOUT_SELECT_PORTB = "GENCLK";
2254 parameter DIVR = 4'b0000;
2255 parameter DIVF = 7'b0000000;
2256 parameter DIVQ = 3'b000;
2257 parameter FILTER_RANGE = 3'b000;
2258 parameter ENABLE_ICEGATE_PORTA = 1'b0;
2259 parameter ENABLE_ICEGATE_PORTB = 1'b0;
2260 parameter TEST_MODE = 1'b0;
2261 parameter EXTERNAL_DIVIDE_FACTOR = 1;
2262 endmodule
2263
2264 (* blackbox *)
2265 module SB_PLL40_2F_CORE (
2266 input REFERENCECLK,
2267 output PLLOUTCOREA,
2268 output PLLOUTGLOBALA,
2269 output PLLOUTCOREB,
2270 output PLLOUTGLOBALB,
2271 input EXTFEEDBACK,
2272 input [7:0] DYNAMICDELAY,
2273 output LOCK,
2274 input BYPASS,
2275 input RESETB,
2276 input LATCHINPUTVALUE,
2277 output SDO,
2278 input SDI,
2279 input SCLK
2280 );
2281 parameter FEEDBACK_PATH = "SIMPLE";
2282 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
2283 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
2284 parameter SHIFTREG_DIV_MODE = 1'b0;
2285 parameter FDA_FEEDBACK = 4'b0000;
2286 parameter FDA_RELATIVE = 4'b0000;
2287 parameter PLLOUT_SELECT_PORTA = "GENCLK";
2288 parameter PLLOUT_SELECT_PORTB = "GENCLK";
2289 parameter DIVR = 4'b0000;
2290 parameter DIVF = 7'b0000000;
2291 parameter DIVQ = 3'b000;
2292 parameter FILTER_RANGE = 3'b000;
2293 parameter ENABLE_ICEGATE_PORTA = 1'b0;
2294 parameter ENABLE_ICEGATE_PORTB = 1'b0;
2295 parameter TEST_MODE = 1'b0;
2296 parameter EXTERNAL_DIVIDE_FACTOR = 1;
2297 endmodule
2298
2299 (* blackbox *)
2300 module SB_PLL40_2F_PAD (
2301 input PACKAGEPIN,
2302 output PLLOUTCOREA,
2303 output PLLOUTGLOBALA,
2304 output PLLOUTCOREB,
2305 output PLLOUTGLOBALB,
2306 input EXTFEEDBACK,
2307 input [7:0] DYNAMICDELAY,
2308 output LOCK,
2309 input BYPASS,
2310 input RESETB,
2311 input LATCHINPUTVALUE,
2312 output SDO,
2313 input SDI,
2314 input SCLK
2315 );
2316 parameter FEEDBACK_PATH = "SIMPLE";
2317 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
2318 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
2319 parameter SHIFTREG_DIV_MODE = 2'b00;
2320 parameter FDA_FEEDBACK = 4'b0000;
2321 parameter FDA_RELATIVE = 4'b0000;
2322 parameter PLLOUT_SELECT_PORTA = "GENCLK";
2323 parameter PLLOUT_SELECT_PORTB = "GENCLK";
2324 parameter DIVR = 4'b0000;
2325 parameter DIVF = 7'b0000000;
2326 parameter DIVQ = 3'b000;
2327 parameter FILTER_RANGE = 3'b000;
2328 parameter ENABLE_ICEGATE_PORTA = 1'b0;
2329 parameter ENABLE_ICEGATE_PORTB = 1'b0;
2330 parameter TEST_MODE = 1'b0;
2331 parameter EXTERNAL_DIVIDE_FACTOR = 1;
2332 endmodule
2333
2334 // SiliconBlue Device Configuration Cells
2335
2336 (* blackbox, keep *)
2337 module SB_WARMBOOT (
2338 input BOOT,
2339 input S1,
2340 input S0
2341 );
2342 endmodule
2343
2344 module SB_SPRAM256KA (
2345 input [13:0] ADDRESS,
2346 input [15:0] DATAIN,
2347 input [3:0] MASKWREN,
2348 input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
2349 output reg [15:0] DATAOUT
2350 );
2351 `ifndef BLACKBOX
2352 `ifndef EQUIV
2353 reg [15:0] mem [0:16383];
2354 wire off = SLEEP || !POWEROFF;
2355 integer i;
2356
2357 always @(negedge POWEROFF) begin
2358 for (i = 0; i <= 16383; i = i+1)
2359 mem[i] = 'bx;
2360 end
2361
2362 always @(posedge CLOCK, posedge off) begin
2363 if (off) begin
2364 DATAOUT <= 0;
2365 end else
2366 if (STANDBY) begin
2367 DATAOUT <= 'bx;
2368 end else
2369 if (CHIPSELECT) begin
2370 if (!WREN) begin
2371 DATAOUT <= mem[ADDRESS];
2372 end else begin
2373 if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0];
2374 if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4];
2375 if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8];
2376 if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12];
2377 DATAOUT <= 'bx;
2378 end
2379 end
2380 end
2381 `endif
2382 `endif
2383 `ifdef ICE40_U
2384 specify
2385 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13169-L13182
2386 $setup(posedge ADDRESS, posedge CLOCK, 268);
2387 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13183
2388 $setup(CHIPSELECT, posedge CLOCK, 404);
2389 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13184-L13199
2390 $setup(DATAIN, posedge CLOCK, 143);
2391 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13200-L13203
2392 $setup(MASKWREN, posedge CLOCK, 143);
2393 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13167
2394 //$setup(negedge SLEEP, posedge CLOCK, 41505);
2395 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13167
2396 //$setup(negedge STANDBY, posedge CLOCK, 1715);
2397 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13206
2398 $setup(WREN, posedge CLOCK, 289);
2399 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13207-L13222
2400 (posedge CLOCK => (DATAOUT : 16'bx)) = 1821;
2401 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13223-L13238
2402 (posedge SLEEP => (DATAOUT : 16'b0)) = 1099;
2403 endspecify
2404 `endif
2405 endmodule
2406
2407 (* blackbox *)
2408 module SB_HFOSC(
2409 input TRIM0,
2410 input TRIM1,
2411 input TRIM2,
2412 input TRIM3,
2413 input TRIM4,
2414 input TRIM5,
2415 input TRIM6,
2416 input TRIM7,
2417 input TRIM8,
2418 input TRIM9,
2419 input CLKHFPU,
2420 input CLKHFEN,
2421 output CLKHF
2422 );
2423 parameter TRIM_EN = "0b0";
2424 parameter CLKHF_DIV = "0b00";
2425 endmodule
2426
2427 (* blackbox *)
2428 module SB_LFOSC(
2429 input CLKLFPU,
2430 input CLKLFEN,
2431 output CLKLF
2432 );
2433 endmodule
2434
2435 (* blackbox *)
2436 module SB_RGBA_DRV(
2437 input CURREN,
2438 input RGBLEDEN,
2439 input RGB0PWM,
2440 input RGB1PWM,
2441 input RGB2PWM,
2442 output RGB0,
2443 output RGB1,
2444 output RGB2
2445 );
2446 parameter CURRENT_MODE = "0b0";
2447 parameter RGB0_CURRENT = "0b000000";
2448 parameter RGB1_CURRENT = "0b000000";
2449 parameter RGB2_CURRENT = "0b000000";
2450 endmodule
2451
2452 (* blackbox *)
2453 module SB_LED_DRV_CUR(
2454 input EN,
2455 output LEDPU
2456 );
2457 endmodule
2458
2459 (* blackbox *)
2460 module SB_RGB_DRV(
2461 input RGBLEDEN,
2462 input RGB0PWM,
2463 input RGB1PWM,
2464 input RGB2PWM,
2465 input RGBPU,
2466 output RGB0,
2467 output RGB1,
2468 output RGB2
2469 );
2470 parameter CURRENT_MODE = "0b0";
2471 parameter RGB0_CURRENT = "0b000000";
2472 parameter RGB1_CURRENT = "0b000000";
2473 parameter RGB2_CURRENT = "0b000000";
2474 endmodule
2475
2476 (* blackbox *)
2477 module SB_I2C(
2478 input SBCLKI,
2479 input SBRWI,
2480 input SBSTBI,
2481 input SBADRI7,
2482 input SBADRI6,
2483 input SBADRI5,
2484 input SBADRI4,
2485 input SBADRI3,
2486 input SBADRI2,
2487 input SBADRI1,
2488 input SBADRI0,
2489 input SBDATI7,
2490 input SBDATI6,
2491 input SBDATI5,
2492 input SBDATI4,
2493 input SBDATI3,
2494 input SBDATI2,
2495 input SBDATI1,
2496 input SBDATI0,
2497 input SCLI,
2498 input SDAI,
2499 output SBDATO7,
2500 output SBDATO6,
2501 output SBDATO5,
2502 output SBDATO4,
2503 output SBDATO3,
2504 output SBDATO2,
2505 output SBDATO1,
2506 output SBDATO0,
2507 output SBACKO,
2508 output I2CIRQ,
2509 output I2CWKUP,
2510 output SCLO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
2511 output SCLOE,
2512 output SDAO,
2513 output SDAOE
2514 );
2515 parameter I2C_SLAVE_INIT_ADDR = "0b1111100001";
2516 parameter BUS_ADDR74 = "0b0001";
2517 endmodule
2518
2519 (* blackbox *)
2520 module SB_SPI (
2521 input SBCLKI,
2522 input SBRWI,
2523 input SBSTBI,
2524 input SBADRI7,
2525 input SBADRI6,
2526 input SBADRI5,
2527 input SBADRI4,
2528 input SBADRI3,
2529 input SBADRI2,
2530 input SBADRI1,
2531 input SBADRI0,
2532 input SBDATI7,
2533 input SBDATI6,
2534 input SBDATI5,
2535 input SBDATI4,
2536 input SBDATI3,
2537 input SBDATI2,
2538 input SBDATI1,
2539 input SBDATI0,
2540 input MI,
2541 input SI,
2542 input SCKI,
2543 input SCSNI,
2544 output SBDATO7,
2545 output SBDATO6,
2546 output SBDATO5,
2547 output SBDATO4,
2548 output SBDATO3,
2549 output SBDATO2,
2550 output SBDATO1,
2551 output SBDATO0,
2552 output SBACKO,
2553 output SPIIRQ,
2554 output SPIWKUP,
2555 output SO,
2556 output SOE,
2557 output MO,
2558 output MOE,
2559 output SCKO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
2560 output SCKOE,
2561 output MCSNO3,
2562 output MCSNO2,
2563 output MCSNO1,
2564 output MCSNO0,
2565 output MCSNOE3,
2566 output MCSNOE2,
2567 output MCSNOE1,
2568 output MCSNOE0
2569 );
2570 parameter BUS_ADDR74 = "0b0000";
2571 endmodule
2572
2573 (* blackbox *)
2574 module SB_LEDDA_IP(
2575 input LEDDCS,
2576 input LEDDCLK,
2577 input LEDDDAT7,
2578 input LEDDDAT6,
2579 input LEDDDAT5,
2580 input LEDDDAT4,
2581 input LEDDDAT3,
2582 input LEDDDAT2,
2583 input LEDDDAT1,
2584 input LEDDDAT0,
2585 input LEDDADDR3,
2586 input LEDDADDR2,
2587 input LEDDADDR1,
2588 input LEDDADDR0,
2589 input LEDDDEN,
2590 input LEDDEXE,
2591 input LEDDRST,
2592 output PWMOUT0,
2593 output PWMOUT1,
2594 output PWMOUT2,
2595 output LEDDON
2596 );
2597 endmodule
2598
2599 (* blackbox *)
2600 module SB_FILTER_50NS(
2601 input FILTERIN,
2602 output FILTEROUT
2603 );
2604 endmodule
2605
2606 module SB_IO_I3C (
2607 inout PACKAGE_PIN,
2608 input LATCH_INPUT_VALUE,
2609 input CLOCK_ENABLE,
2610 input INPUT_CLK,
2611 input OUTPUT_CLK,
2612 input OUTPUT_ENABLE,
2613 input D_OUT_0,
2614 input D_OUT_1,
2615 output D_IN_0,
2616 output D_IN_1,
2617 input PU_ENB,
2618 input WEAK_PU_ENB
2619 );
2620 parameter [5:0] PIN_TYPE = 6'b000000;
2621 parameter [0:0] PULLUP = 1'b0;
2622 parameter [0:0] WEAK_PULLUP = 1'b0;
2623 parameter [0:0] NEG_TRIGGER = 1'b0;
2624 parameter IO_STANDARD = "SB_LVCMOS";
2625
2626 `ifndef BLACKBOX
2627 reg dout, din_0, din_1;
2628 reg din_q_0, din_q_1;
2629 reg dout_q_0, dout_q_1;
2630 reg outena_q;
2631
2632 generate if (!NEG_TRIGGER) begin
2633 always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
2634 always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
2635 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
2636 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
2637 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
2638 end else begin
2639 always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
2640 always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
2641 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
2642 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
2643 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
2644 end endgenerate
2645
2646 always @* begin
2647 if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
2648 din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
2649 din_1 = din_q_1;
2650 end
2651
2652 // work around simulation glitches on dout in DDR mode
2653 reg outclk_delayed_1;
2654 reg outclk_delayed_2;
2655 always @* outclk_delayed_1 <= OUTPUT_CLK;
2656 always @* outclk_delayed_2 <= outclk_delayed_1;
2657
2658 always @* begin
2659 if (PIN_TYPE[3])
2660 dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
2661 else
2662 dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
2663 end
2664
2665 assign D_IN_0 = din_0, D_IN_1 = din_1;
2666
2667 generate
2668 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
2669 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
2670 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
2671 endgenerate
2672 `endif
2673 endmodule
2674
2675 module SB_IO_OD (
2676 inout PACKAGEPIN,
2677 input LATCHINPUTVALUE,
2678 input CLOCKENABLE,
2679 input INPUTCLK,
2680 input OUTPUTCLK,
2681 input OUTPUTENABLE,
2682 input DOUT1,
2683 input DOUT0,
2684 output DIN1,
2685 output DIN0
2686 );
2687 parameter [5:0] PIN_TYPE = 6'b000000;
2688 parameter [0:0] NEG_TRIGGER = 1'b0;
2689
2690 `ifndef BLACKBOX
2691 reg dout, din_0, din_1;
2692 reg din_q_0, din_q_1;
2693 reg dout_q_0, dout_q_1;
2694 reg outena_q;
2695
2696 generate if (!NEG_TRIGGER) begin
2697 always @(posedge INPUTCLK) if (CLOCKENABLE) din_q_0 <= PACKAGEPIN;
2698 always @(negedge INPUTCLK) if (CLOCKENABLE) din_q_1 <= PACKAGEPIN;
2699 always @(posedge OUTPUTCLK) if (CLOCKENABLE) dout_q_0 <= DOUT0;
2700 always @(negedge OUTPUTCLK) if (CLOCKENABLE) dout_q_1 <= DOUT1;
2701 always @(posedge OUTPUTCLK) if (CLOCKENABLE) outena_q <= OUTPUTENABLE;
2702 end else begin
2703 always @(negedge INPUTCLK) if (CLOCKENABLE) din_q_0 <= PACKAGEPIN;
2704 always @(posedge INPUTCLK) if (CLOCKENABLE) din_q_1 <= PACKAGEPIN;
2705 always @(negedge OUTPUTCLK) if (CLOCKENABLE) dout_q_0 <= DOUT0;
2706 always @(posedge OUTPUTCLK) if (CLOCKENABLE) dout_q_1 <= DOUT1;
2707 always @(negedge OUTPUTCLK) if (CLOCKENABLE) outena_q <= OUTPUTENABLE;
2708 end endgenerate
2709
2710 always @* begin
2711 if (!PIN_TYPE[1] || !LATCHINPUTVALUE)
2712 din_0 = PIN_TYPE[0] ? PACKAGEPIN : din_q_0;
2713 din_1 = din_q_1;
2714 end
2715
2716 // work around simulation glitches on dout in DDR mode
2717 reg outclk_delayed_1;
2718 reg outclk_delayed_2;
2719 always @* outclk_delayed_1 <= OUTPUTCLK;
2720 always @* outclk_delayed_2 <= outclk_delayed_1;
2721
2722 always @* begin
2723 if (PIN_TYPE[3])
2724 dout = PIN_TYPE[2] ? !dout_q_0 : DOUT0;
2725 else
2726 dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
2727 end
2728
2729 assign DIN0 = din_0, DIN1 = din_1;
2730
2731 generate
2732 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGEPIN = dout ? 1'bz : 1'b0;
2733 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGEPIN = OUTPUTENABLE ? (dout ? 1'bz : 1'b0) : 1'bz;
2734 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGEPIN = outena_q ? (dout ? 1'bz : 1'b0) : 1'bz;
2735 endgenerate
2736 `endif
2737 endmodule
2738
2739 module SB_MAC16 (
2740 input CLK, CE,
2741 input [15:0] C, A, B, D,
2742 input AHOLD, BHOLD, CHOLD, DHOLD,
2743 input IRSTTOP, IRSTBOT,
2744 input ORSTTOP, ORSTBOT,
2745 input OLOADTOP, OLOADBOT,
2746 input ADDSUBTOP, ADDSUBBOT,
2747 input OHOLDTOP, OHOLDBOT,
2748 input CI, ACCUMCI, SIGNEXTIN,
2749 output [31:0] O,
2750 output CO, ACCUMCO, SIGNEXTOUT
2751 );
2752 parameter [0:0] NEG_TRIGGER = 0;
2753 parameter [0:0] C_REG = 0;
2754 parameter [0:0] A_REG = 0;
2755 parameter [0:0] B_REG = 0;
2756 parameter [0:0] D_REG = 0;
2757 parameter [0:0] TOP_8x8_MULT_REG = 0;
2758 parameter [0:0] BOT_8x8_MULT_REG = 0;
2759 parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
2760 parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
2761 parameter [1:0] TOPOUTPUT_SELECT = 0;
2762 parameter [1:0] TOPADDSUB_LOWERINPUT = 0;
2763 parameter [0:0] TOPADDSUB_UPPERINPUT = 0;
2764 parameter [1:0] TOPADDSUB_CARRYSELECT = 0;
2765 parameter [1:0] BOTOUTPUT_SELECT = 0;
2766 parameter [1:0] BOTADDSUB_LOWERINPUT = 0;
2767 parameter [0:0] BOTADDSUB_UPPERINPUT = 0;
2768 parameter [1:0] BOTADDSUB_CARRYSELECT = 0;
2769 parameter [0:0] MODE_8x8 = 0;
2770 parameter [0:0] A_SIGNED = 0;
2771 parameter [0:0] B_SIGNED = 0;
2772
2773 wire clock = CLK ^ NEG_TRIGGER;
2774
2775 // internal wires, compare Figure on page 133 of ICE Technology Library 3.0 and Fig 2 on page 2 of Lattice TN1295-DSP
2776 // http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201608.pdf
2777 // https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/AD/DSPFunctionUsageGuideforICE40Devices.ashx
2778 wire [15:0] iA, iB, iC, iD;
2779 wire [15:0] iF, iJ, iK, iG;
2780 wire [31:0] iL, iH;
2781 wire [15:0] iW, iX, iP, iQ;
2782 wire [15:0] iY, iZ, iR, iS;
2783 wire HCI, LCI, LCO;
2784
2785 // Regs C and A
2786 reg [15:0] rC, rA;
2787 always @(posedge clock, posedge IRSTTOP) begin
2788 if (IRSTTOP) begin
2789 rC <= 0;
2790 rA <= 0;
2791 end else if (CE) begin
2792 if (!CHOLD) rC <= C;
2793 if (!AHOLD) rA <= A;
2794 end
2795 end
2796 assign iC = C_REG ? rC : C;
2797 assign iA = A_REG ? rA : A;
2798
2799 // Regs B and D
2800 reg [15:0] rB, rD;
2801 always @(posedge clock, posedge IRSTBOT) begin
2802 if (IRSTBOT) begin
2803 rB <= 0;
2804 rD <= 0;
2805 end else if (CE) begin
2806 if (!BHOLD) rB <= B;
2807 if (!DHOLD) rD <= D;
2808 end
2809 end
2810 assign iB = B_REG ? rB : B;
2811 assign iD = D_REG ? rD : D;
2812
2813 // Multiplier Stage
2814 wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
2815 wire [15:0] Ah, Al, Bh, Bl;
2816 assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]};
2817 assign Al = {A_SIGNED && MODE_8x8 ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
2818 assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]};
2819 assign Bl = {B_SIGNED && MODE_8x8 ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
2820 assign p_Ah_Bh = Ah * Bh; // F
2821 assign p_Al_Bh = {8'b0, Al[7:0]} * Bh; // J
2822 assign p_Ah_Bl = Ah * {8'b0, Bl[7:0]}; // K
2823 assign p_Al_Bl = Al * Bl; // G
2824
2825 // Regs F and J
2826 reg [15:0] rF, rJ;
2827 always @(posedge clock, posedge IRSTTOP) begin
2828 if (IRSTTOP) begin
2829 rF <= 0;
2830 rJ <= 0;
2831 end else if (CE) begin
2832 rF <= p_Ah_Bh;
2833 if (!MODE_8x8) rJ <= p_Al_Bh;
2834 end
2835 end
2836 assign iF = TOP_8x8_MULT_REG ? rF : p_Ah_Bh;
2837 assign iJ = PIPELINE_16x16_MULT_REG1 ? rJ : p_Al_Bh;
2838
2839 // Regs K and G
2840 reg [15:0] rK, rG;
2841 always @(posedge clock, posedge IRSTBOT) begin
2842 if (IRSTBOT) begin
2843 rK <= 0;
2844 rG <= 0;
2845 end else if (CE) begin
2846 if (!MODE_8x8) rK <= p_Ah_Bl;
2847 rG <= p_Al_Bl;
2848 end
2849 end
2850 assign iK = PIPELINE_16x16_MULT_REG1 ? rK : p_Ah_Bl;
2851 assign iG = BOT_8x8_MULT_REG ? rG : p_Al_Bl;
2852
2853 // Adder Stage
2854 wire [23:0] iK_e = {A_SIGNED ? {8{iK[15]}} : 8'b0, iK};
2855 wire [23:0] iJ_e = {B_SIGNED ? {8{iJ[15]}} : 8'b0, iJ};
2856 assign iL = iG + (iK_e << 8) + (iJ_e << 8) + (iF << 16);
2857
2858 // Reg H
2859 reg [31:0] rH;
2860 always @(posedge clock, posedge IRSTBOT) begin
2861 if (IRSTBOT) begin
2862 rH <= 0;
2863 end else if (CE) begin
2864 if (!MODE_8x8) rH <= iL;
2865 end
2866 end
2867 assign iH = PIPELINE_16x16_MULT_REG2 ? rH : iL;
2868
2869 // Hi Output Stage
2870 wire [15:0] XW, Oh;
2871 reg [15:0] rQ;
2872 assign iW = TOPADDSUB_UPPERINPUT ? iC : iQ;
2873 assign iX = (TOPADDSUB_LOWERINPUT == 0) ? iA : (TOPADDSUB_LOWERINPUT == 1) ? iF : (TOPADDSUB_LOWERINPUT == 2) ? iH[31:16] : {16{iZ[15]}};
2874 assign {ACCUMCO, XW} = iX + (iW ^ {16{ADDSUBTOP}}) + HCI;
2875 assign CO = ACCUMCO ^ ADDSUBTOP;
2876 assign iP = OLOADTOP ? iC : XW ^ {16{ADDSUBTOP}};
2877 always @(posedge clock, posedge ORSTTOP) begin
2878 if (ORSTTOP) begin
2879 rQ <= 0;
2880 end else if (CE) begin
2881 if (!OHOLDTOP) rQ <= iP;
2882 end
2883 end
2884 assign iQ = rQ;
2885 assign Oh = (TOPOUTPUT_SELECT == 0) ? iP : (TOPOUTPUT_SELECT == 1) ? iQ : (TOPOUTPUT_SELECT == 2) ? iF : iH[31:16];
2886 assign HCI = (TOPADDSUB_CARRYSELECT == 0) ? 1'b0 : (TOPADDSUB_CARRYSELECT == 1) ? 1'b1 : (TOPADDSUB_CARRYSELECT == 2) ? LCO : LCO ^ ADDSUBBOT;
2887 assign SIGNEXTOUT = iX[15];
2888
2889 // Lo Output Stage
2890 wire [15:0] YZ, Ol;
2891 reg [15:0] rS;
2892 assign iY = BOTADDSUB_UPPERINPUT ? iD : iS;
2893 assign iZ = (BOTADDSUB_LOWERINPUT == 0) ? iB : (BOTADDSUB_LOWERINPUT == 1) ? iG : (BOTADDSUB_LOWERINPUT == 2) ? iH[15:0] : {16{SIGNEXTIN}};
2894 assign {LCO, YZ} = iZ + (iY ^ {16{ADDSUBBOT}}) + LCI;
2895 assign iR = OLOADBOT ? iD : YZ ^ {16{ADDSUBBOT}};
2896 always @(posedge clock, posedge ORSTBOT) begin
2897 if (ORSTBOT) begin
2898 rS <= 0;
2899 end else if (CE) begin
2900 if (!OHOLDBOT) rS <= iR;
2901 end
2902 end
2903 assign iS = rS;
2904 assign Ol = (BOTOUTPUT_SELECT == 0) ? iR : (BOTOUTPUT_SELECT == 1) ? iS : (BOTOUTPUT_SELECT == 2) ? iG : iH[15:0];
2905 assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI;
2906 assign O = {Oh, Ol};
2907 endmodule
2908
2909 // Post-place-and-route RAM model
2910 module ICESTORM_RAM(
2911 output RDATA_15, RDATA_14, RDATA_13, RDATA_12, RDATA_11, RDATA_10, RDATA_9, RDATA_8, RDATA_7, RDATA_6, RDATA_5, RDATA_4, RDATA_3, RDATA_2, RDATA_1, RDATA_0,
2912 input RCLK, RCLKE, RE,
2913 input RADDR_10, RADDR_9, RADDR_8, RADDR_7, RADDR_6, RADDR_5, RADDR_4, RADDR_3, RADDR_2, RADDR_1, RADDR_0,
2914 input WCLK, WCLKE, WE,
2915 input WADDR_10, WADDR_9, WADDR_8, WADDR_7, WADDR_6, WADDR_5, WADDR_4, WADDR_3, WADDR_2, WADDR_1, WADDR_0,
2916 input MASK_15, MASK_14, MASK_13, MASK_12, MASK_11, MASK_10, MASK_9, MASK_8, MASK_7, MASK_6, MASK_5, MASK_4, MASK_3, MASK_2, MASK_1, MASK_0,
2917 input WDATA_15, WDATA_14, WDATA_13, WDATA_12, WDATA_11, WDATA_10, WDATA_9, WDATA_8, WDATA_7, WDATA_6, WDATA_5, WDATA_4, WDATA_3, WDATA_2, WDATA_1, WDATA_0
2918 );
2919 parameter WRITE_MODE = 0;
2920 parameter READ_MODE = 0;
2921
2922 parameter NEG_CLK_R = 1'b0;
2923 parameter NEG_CLK_W = 1'b0;
2924
2925 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2926 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2927 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2928 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2929 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2930 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2931 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2932 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2933 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2934 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2935 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2936 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2937 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2938 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2939 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2940 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2941
2942 // Pull-down and pull-up functions
2943 function pd;
2944 input x;
2945 begin
2946 pd = (x === 1'bz) ? 1'b0 : x;
2947 end
2948 endfunction
2949
2950 function pu;
2951 input x;
2952 begin
2953 pu = (x === 1'bz) ? 1'b1 : x;
2954 end
2955 endfunction
2956
2957 SB_RAM40_4K #(
2958 .WRITE_MODE(WRITE_MODE),
2959 .READ_MODE (READ_MODE ),
2960 .INIT_0 (INIT_0 ),
2961 .INIT_1 (INIT_1 ),
2962 .INIT_2 (INIT_2 ),
2963 .INIT_3 (INIT_3 ),
2964 .INIT_4 (INIT_4 ),
2965 .INIT_5 (INIT_5 ),
2966 .INIT_6 (INIT_6 ),
2967 .INIT_7 (INIT_7 ),
2968 .INIT_8 (INIT_8 ),
2969 .INIT_9 (INIT_9 ),
2970 .INIT_A (INIT_A ),
2971 .INIT_B (INIT_B ),
2972 .INIT_C (INIT_C ),
2973 .INIT_D (INIT_D ),
2974 .INIT_E (INIT_E ),
2975 .INIT_F (INIT_F )
2976 ) RAM (
2977 .RDATA({RDATA_15, RDATA_14, RDATA_13, RDATA_12, RDATA_11, RDATA_10, RDATA_9, RDATA_8, RDATA_7, RDATA_6, RDATA_5, RDATA_4, RDATA_3, RDATA_2, RDATA_1, RDATA_0}),
2978 .RCLK (pd(RCLK) ^ NEG_CLK_R),
2979 .RCLKE(pu(RCLKE)),
2980 .RE (pd(RE)),
2981 .RADDR({pd(RADDR_10), pd(RADDR_9), pd(RADDR_8), pd(RADDR_7), pd(RADDR_6), pd(RADDR_5), pd(RADDR_4), pd(RADDR_3), pd(RADDR_2), pd(RADDR_1), pd(RADDR_0)}),
2982 .WCLK (pd(WCLK) ^ NEG_CLK_W),
2983 .WCLKE(pu(WCLKE)),
2984 .WE (pd(WE)),
2985 .WADDR({pd(WADDR_10), pd(WADDR_9), pd(WADDR_8), pd(WADDR_7), pd(WADDR_6), pd(WADDR_5), pd(WADDR_4), pd(WADDR_3), pd(WADDR_2), pd(WADDR_1), pd(WADDR_0)}),
2986 .MASK ({pd(MASK_15), pd(MASK_14), pd(MASK_13), pd(MASK_12), pd(MASK_11), pd(MASK_10), pd(MASK_9), pd(MASK_8),
2987 pd(MASK_7), pd(MASK_6), pd(MASK_5), pd(MASK_4), pd(MASK_3), pd(MASK_2), pd(MASK_1), pd(MASK_0)}),
2988 .WDATA({pd(WDATA_15), pd(WDATA_14), pd(WDATA_13), pd(WDATA_12), pd(WDATA_11), pd(WDATA_10), pd(WDATA_9), pd(WDATA_8),
2989 pd(WDATA_7), pd(WDATA_6), pd(WDATA_5), pd(WDATA_4), pd(WDATA_3), pd(WDATA_2), pd(WDATA_1), pd(WDATA_0)})
2990 );
2991
2992 `ifdef TIMING
2993 specify
2994 (RCLK => RDATA_15) = (0:0:0, 0:0:0);
2995 (RCLK => RDATA_14) = (0:0:0, 0:0:0);
2996 (RCLK => RDATA_13) = (0:0:0, 0:0:0);
2997 (RCLK => RDATA_12) = (0:0:0, 0:0:0);
2998 (RCLK => RDATA_11) = (0:0:0, 0:0:0);
2999 (RCLK => RDATA_10) = (0:0:0, 0:0:0);
3000 (RCLK => RDATA_9) = (0:0:0, 0:0:0);
3001 (RCLK => RDATA_8) = (0:0:0, 0:0:0);
3002 (RCLK => RDATA_7) = (0:0:0, 0:0:0);
3003 (RCLK => RDATA_6) = (0:0:0, 0:0:0);
3004 (RCLK => RDATA_5) = (0:0:0, 0:0:0);
3005 (RCLK => RDATA_4) = (0:0:0, 0:0:0);
3006 (RCLK => RDATA_3) = (0:0:0, 0:0:0);
3007 (RCLK => RDATA_2) = (0:0:0, 0:0:0);
3008 (RCLK => RDATA_1) = (0:0:0, 0:0:0);
3009 (RCLK => RDATA_0) = (0:0:0, 0:0:0);
3010 $setuphold(posedge RCLK, posedge RCLKE, 0:0:0, 0:0:0);
3011 $setuphold(posedge RCLK, negedge RCLKE, 0:0:0, 0:0:0);
3012 $setuphold(negedge RCLK, posedge RCLKE, 0:0:0, 0:0:0);
3013 $setuphold(negedge RCLK, negedge RCLKE, 0:0:0, 0:0:0);
3014 $setuphold(posedge RCLK, posedge RE, 0:0:0, 0:0:0);
3015 $setuphold(posedge RCLK, negedge RE, 0:0:0, 0:0:0);
3016 $setuphold(negedge RCLK, posedge RE, 0:0:0, 0:0:0);
3017 $setuphold(negedge RCLK, negedge RE, 0:0:0, 0:0:0);
3018 $setuphold(posedge RCLK, posedge RADDR_10, 0:0:0, 0:0:0);
3019 $setuphold(posedge RCLK, negedge RADDR_10, 0:0:0, 0:0:0);
3020 $setuphold(negedge RCLK, posedge RADDR_10, 0:0:0, 0:0:0);
3021 $setuphold(negedge RCLK, negedge RADDR_10, 0:0:0, 0:0:0);
3022 $setuphold(posedge RCLK, posedge RADDR_9, 0:0:0, 0:0:0);
3023 $setuphold(posedge RCLK, negedge RADDR_9, 0:0:0, 0:0:0);
3024 $setuphold(negedge RCLK, posedge RADDR_9, 0:0:0, 0:0:0);
3025 $setuphold(negedge RCLK, negedge RADDR_9, 0:0:0, 0:0:0);
3026 $setuphold(posedge RCLK, posedge RADDR_8, 0:0:0, 0:0:0);
3027 $setuphold(posedge RCLK, negedge RADDR_8, 0:0:0, 0:0:0);
3028 $setuphold(negedge RCLK, posedge RADDR_8, 0:0:0, 0:0:0);
3029 $setuphold(negedge RCLK, negedge RADDR_8, 0:0:0, 0:0:0);
3030 $setuphold(posedge RCLK, posedge RADDR_7, 0:0:0, 0:0:0);
3031 $setuphold(posedge RCLK, negedge RADDR_7, 0:0:0, 0:0:0);
3032 $setuphold(negedge RCLK, posedge RADDR_7, 0:0:0, 0:0:0);
3033 $setuphold(negedge RCLK, negedge RADDR_7, 0:0:0, 0:0:0);
3034 $setuphold(posedge RCLK, posedge RADDR_6, 0:0:0, 0:0:0);
3035 $setuphold(posedge RCLK, negedge RADDR_6, 0:0:0, 0:0:0);
3036 $setuphold(negedge RCLK, posedge RADDR_6, 0:0:0, 0:0:0);
3037 $setuphold(negedge RCLK, negedge RADDR_6, 0:0:0, 0:0:0);
3038 $setuphold(posedge RCLK, posedge RADDR_5, 0:0:0, 0:0:0);
3039 $setuphold(posedge RCLK, negedge RADDR_5, 0:0:0, 0:0:0);
3040 $setuphold(negedge RCLK, posedge RADDR_5, 0:0:0, 0:0:0);
3041 $setuphold(negedge RCLK, negedge RADDR_5, 0:0:0, 0:0:0);
3042 $setuphold(posedge RCLK, posedge RADDR_4, 0:0:0, 0:0:0);
3043 $setuphold(posedge RCLK, negedge RADDR_4, 0:0:0, 0:0:0);
3044 $setuphold(negedge RCLK, posedge RADDR_4, 0:0:0, 0:0:0);
3045 $setuphold(negedge RCLK, negedge RADDR_4, 0:0:0, 0:0:0);
3046 $setuphold(posedge RCLK, posedge RADDR_3, 0:0:0, 0:0:0);
3047 $setuphold(posedge RCLK, negedge RADDR_3, 0:0:0, 0:0:0);
3048 $setuphold(negedge RCLK, posedge RADDR_3, 0:0:0, 0:0:0);
3049 $setuphold(negedge RCLK, negedge RADDR_3, 0:0:0, 0:0:0);
3050 $setuphold(posedge RCLK, posedge RADDR_2, 0:0:0, 0:0:0);
3051 $setuphold(posedge RCLK, negedge RADDR_2, 0:0:0, 0:0:0);
3052 $setuphold(negedge RCLK, posedge RADDR_2, 0:0:0, 0:0:0);
3053 $setuphold(negedge RCLK, negedge RADDR_2, 0:0:0, 0:0:0);
3054 $setuphold(posedge RCLK, posedge RADDR_1, 0:0:0, 0:0:0);
3055 $setuphold(posedge RCLK, negedge RADDR_1, 0:0:0, 0:0:0);
3056 $setuphold(negedge RCLK, posedge RADDR_1, 0:0:0, 0:0:0);
3057 $setuphold(negedge RCLK, negedge RADDR_1, 0:0:0, 0:0:0);
3058 $setuphold(posedge RCLK, posedge RADDR_0, 0:0:0, 0:0:0);
3059 $setuphold(posedge RCLK, negedge RADDR_0, 0:0:0, 0:0:0);
3060 $setuphold(negedge RCLK, posedge RADDR_0, 0:0:0, 0:0:0);
3061 $setuphold(negedge RCLK, negedge RADDR_0, 0:0:0, 0:0:0);
3062 $setuphold(posedge WCLK, posedge WCLKE, 0:0:0, 0:0:0);
3063 $setuphold(posedge WCLK, negedge WCLKE, 0:0:0, 0:0:0);
3064 $setuphold(negedge WCLK, posedge WCLKE, 0:0:0, 0:0:0);
3065 $setuphold(negedge WCLK, negedge WCLKE, 0:0:0, 0:0:0);
3066 $setuphold(posedge WCLK, posedge WE, 0:0:0, 0:0:0);
3067 $setuphold(posedge WCLK, negedge WE, 0:0:0, 0:0:0);
3068 $setuphold(negedge WCLK, posedge WE, 0:0:0, 0:0:0);
3069 $setuphold(negedge WCLK, negedge WE, 0:0:0, 0:0:0);
3070 $setuphold(posedge WCLK, posedge WADDR_10, 0:0:0, 0:0:0);
3071 $setuphold(posedge WCLK, negedge WADDR_10, 0:0:0, 0:0:0);
3072 $setuphold(negedge WCLK, posedge WADDR_10, 0:0:0, 0:0:0);
3073 $setuphold(negedge WCLK, negedge WADDR_10, 0:0:0, 0:0:0);
3074 $setuphold(posedge WCLK, posedge WADDR_9, 0:0:0, 0:0:0);
3075 $setuphold(posedge WCLK, negedge WADDR_9, 0:0:0, 0:0:0);
3076 $setuphold(negedge WCLK, posedge WADDR_9, 0:0:0, 0:0:0);
3077 $setuphold(negedge WCLK, negedge WADDR_9, 0:0:0, 0:0:0);
3078 $setuphold(posedge WCLK, posedge WADDR_8, 0:0:0, 0:0:0);
3079 $setuphold(posedge WCLK, negedge WADDR_8, 0:0:0, 0:0:0);
3080 $setuphold(negedge WCLK, posedge WADDR_8, 0:0:0, 0:0:0);
3081 $setuphold(negedge WCLK, negedge WADDR_8, 0:0:0, 0:0:0);
3082 $setuphold(posedge WCLK, posedge WADDR_7, 0:0:0, 0:0:0);
3083 $setuphold(posedge WCLK, negedge WADDR_7, 0:0:0, 0:0:0);
3084 $setuphold(negedge WCLK, posedge WADDR_7, 0:0:0, 0:0:0);
3085 $setuphold(negedge WCLK, negedge WADDR_7, 0:0:0, 0:0:0);
3086 $setuphold(posedge WCLK, posedge WADDR_6, 0:0:0, 0:0:0);
3087 $setuphold(posedge WCLK, negedge WADDR_6, 0:0:0, 0:0:0);
3088 $setuphold(negedge WCLK, posedge WADDR_6, 0:0:0, 0:0:0);
3089 $setuphold(negedge WCLK, negedge WADDR_6, 0:0:0, 0:0:0);
3090 $setuphold(posedge WCLK, posedge WADDR_5, 0:0:0, 0:0:0);
3091 $setuphold(posedge WCLK, negedge WADDR_5, 0:0:0, 0:0:0);
3092 $setuphold(negedge WCLK, posedge WADDR_5, 0:0:0, 0:0:0);
3093 $setuphold(negedge WCLK, negedge WADDR_5, 0:0:0, 0:0:0);
3094 $setuphold(posedge WCLK, posedge WADDR_4, 0:0:0, 0:0:0);
3095 $setuphold(posedge WCLK, negedge WADDR_4, 0:0:0, 0:0:0);
3096 $setuphold(negedge WCLK, posedge WADDR_4, 0:0:0, 0:0:0);
3097 $setuphold(negedge WCLK, negedge WADDR_4, 0:0:0, 0:0:0);
3098 $setuphold(posedge WCLK, posedge WADDR_3, 0:0:0, 0:0:0);
3099 $setuphold(posedge WCLK, negedge WADDR_3, 0:0:0, 0:0:0);
3100 $setuphold(negedge WCLK, posedge WADDR_3, 0:0:0, 0:0:0);
3101 $setuphold(negedge WCLK, negedge WADDR_3, 0:0:0, 0:0:0);
3102 $setuphold(posedge WCLK, posedge WADDR_2, 0:0:0, 0:0:0);
3103 $setuphold(posedge WCLK, negedge WADDR_2, 0:0:0, 0:0:0);
3104 $setuphold(negedge WCLK, posedge WADDR_2, 0:0:0, 0:0:0);
3105 $setuphold(negedge WCLK, negedge WADDR_2, 0:0:0, 0:0:0);
3106 $setuphold(posedge WCLK, posedge WADDR_1, 0:0:0, 0:0:0);
3107 $setuphold(posedge WCLK, negedge WADDR_1, 0:0:0, 0:0:0);
3108 $setuphold(negedge WCLK, posedge WADDR_1, 0:0:0, 0:0:0);
3109 $setuphold(negedge WCLK, negedge WADDR_1, 0:0:0, 0:0:0);
3110 $setuphold(posedge WCLK, posedge WADDR_0, 0:0:0, 0:0:0);
3111 $setuphold(posedge WCLK, negedge WADDR_0, 0:0:0, 0:0:0);
3112 $setuphold(negedge WCLK, posedge WADDR_0, 0:0:0, 0:0:0);
3113 $setuphold(negedge WCLK, negedge WADDR_0, 0:0:0, 0:0:0);
3114 $setuphold(posedge WCLK, posedge MASK_15, 0:0:0, 0:0:0);
3115 $setuphold(posedge WCLK, negedge MASK_15, 0:0:0, 0:0:0);
3116 $setuphold(negedge WCLK, posedge MASK_15, 0:0:0, 0:0:0);
3117 $setuphold(negedge WCLK, negedge MASK_15, 0:0:0, 0:0:0);
3118 $setuphold(posedge WCLK, posedge MASK_14, 0:0:0, 0:0:0);
3119 $setuphold(posedge WCLK, negedge MASK_14, 0:0:0, 0:0:0);
3120 $setuphold(negedge WCLK, posedge MASK_14, 0:0:0, 0:0:0);
3121 $setuphold(negedge WCLK, negedge MASK_14, 0:0:0, 0:0:0);
3122 $setuphold(posedge WCLK, posedge MASK_13, 0:0:0, 0:0:0);
3123 $setuphold(posedge WCLK, negedge MASK_13, 0:0:0, 0:0:0);
3124 $setuphold(negedge WCLK, posedge MASK_13, 0:0:0, 0:0:0);
3125 $setuphold(negedge WCLK, negedge MASK_13, 0:0:0, 0:0:0);
3126 $setuphold(posedge WCLK, posedge MASK_12, 0:0:0, 0:0:0);
3127 $setuphold(posedge WCLK, negedge MASK_12, 0:0:0, 0:0:0);
3128 $setuphold(negedge WCLK, posedge MASK_12, 0:0:0, 0:0:0);
3129 $setuphold(negedge WCLK, negedge MASK_12, 0:0:0, 0:0:0);
3130 $setuphold(posedge WCLK, posedge MASK_11, 0:0:0, 0:0:0);
3131 $setuphold(posedge WCLK, negedge MASK_11, 0:0:0, 0:0:0);
3132 $setuphold(negedge WCLK, posedge MASK_11, 0:0:0, 0:0:0);
3133 $setuphold(negedge WCLK, negedge MASK_11, 0:0:0, 0:0:0);
3134 $setuphold(posedge WCLK, posedge MASK_10, 0:0:0, 0:0:0);
3135 $setuphold(posedge WCLK, negedge MASK_10, 0:0:0, 0:0:0);
3136 $setuphold(negedge WCLK, posedge MASK_10, 0:0:0, 0:0:0);
3137 $setuphold(negedge WCLK, negedge MASK_10, 0:0:0, 0:0:0);
3138 $setuphold(posedge WCLK, posedge MASK_9, 0:0:0, 0:0:0);
3139 $setuphold(posedge WCLK, negedge MASK_9, 0:0:0, 0:0:0);
3140 $setuphold(negedge WCLK, posedge MASK_9, 0:0:0, 0:0:0);
3141 $setuphold(negedge WCLK, negedge MASK_9, 0:0:0, 0:0:0);
3142 $setuphold(posedge WCLK, posedge MASK_8, 0:0:0, 0:0:0);
3143 $setuphold(posedge WCLK, negedge MASK_8, 0:0:0, 0:0:0);
3144 $setuphold(negedge WCLK, posedge MASK_8, 0:0:0, 0:0:0);
3145 $setuphold(negedge WCLK, negedge MASK_8, 0:0:0, 0:0:0);
3146 $setuphold(posedge WCLK, posedge MASK_7, 0:0:0, 0:0:0);
3147 $setuphold(posedge WCLK, negedge MASK_7, 0:0:0, 0:0:0);
3148 $setuphold(negedge WCLK, posedge MASK_7, 0:0:0, 0:0:0);
3149 $setuphold(negedge WCLK, negedge MASK_7, 0:0:0, 0:0:0);
3150 $setuphold(posedge WCLK, posedge MASK_6, 0:0:0, 0:0:0);
3151 $setuphold(posedge WCLK, negedge MASK_6, 0:0:0, 0:0:0);
3152 $setuphold(negedge WCLK, posedge MASK_6, 0:0:0, 0:0:0);
3153 $setuphold(negedge WCLK, negedge MASK_6, 0:0:0, 0:0:0);
3154 $setuphold(posedge WCLK, posedge MASK_5, 0:0:0, 0:0:0);
3155 $setuphold(posedge WCLK, negedge MASK_5, 0:0:0, 0:0:0);
3156 $setuphold(negedge WCLK, posedge MASK_5, 0:0:0, 0:0:0);
3157 $setuphold(negedge WCLK, negedge MASK_5, 0:0:0, 0:0:0);
3158 $setuphold(posedge WCLK, posedge MASK_4, 0:0:0, 0:0:0);
3159 $setuphold(posedge WCLK, negedge MASK_4, 0:0:0, 0:0:0);
3160 $setuphold(negedge WCLK, posedge MASK_4, 0:0:0, 0:0:0);
3161 $setuphold(negedge WCLK, negedge MASK_4, 0:0:0, 0:0:0);
3162 $setuphold(posedge WCLK, posedge MASK_3, 0:0:0, 0:0:0);
3163 $setuphold(posedge WCLK, negedge MASK_3, 0:0:0, 0:0:0);
3164 $setuphold(negedge WCLK, posedge MASK_3, 0:0:0, 0:0:0);
3165 $setuphold(negedge WCLK, negedge MASK_3, 0:0:0, 0:0:0);
3166 $setuphold(posedge WCLK, posedge MASK_2, 0:0:0, 0:0:0);
3167 $setuphold(posedge WCLK, negedge MASK_2, 0:0:0, 0:0:0);
3168 $setuphold(negedge WCLK, posedge MASK_2, 0:0:0, 0:0:0);
3169 $setuphold(negedge WCLK, negedge MASK_2, 0:0:0, 0:0:0);
3170 $setuphold(posedge WCLK, posedge MASK_1, 0:0:0, 0:0:0);
3171 $setuphold(posedge WCLK, negedge MASK_1, 0:0:0, 0:0:0);
3172 $setuphold(negedge WCLK, posedge MASK_1, 0:0:0, 0:0:0);
3173 $setuphold(negedge WCLK, negedge MASK_1, 0:0:0, 0:0:0);
3174 $setuphold(posedge WCLK, posedge MASK_0, 0:0:0, 0:0:0);
3175 $setuphold(posedge WCLK, negedge MASK_0, 0:0:0, 0:0:0);
3176 $setuphold(negedge WCLK, posedge MASK_0, 0:0:0, 0:0:0);
3177 $setuphold(negedge WCLK, negedge MASK_0, 0:0:0, 0:0:0);
3178 $setuphold(posedge WCLK, posedge WDATA_15, 0:0:0, 0:0:0);
3179 $setuphold(posedge WCLK, negedge WDATA_15, 0:0:0, 0:0:0);
3180 $setuphold(negedge WCLK, posedge WDATA_15, 0:0:0, 0:0:0);
3181 $setuphold(negedge WCLK, negedge WDATA_15, 0:0:0, 0:0:0);
3182 $setuphold(posedge WCLK, posedge WDATA_14, 0:0:0, 0:0:0);
3183 $setuphold(posedge WCLK, negedge WDATA_14, 0:0:0, 0:0:0);
3184 $setuphold(negedge WCLK, posedge WDATA_14, 0:0:0, 0:0:0);
3185 $setuphold(negedge WCLK, negedge WDATA_14, 0:0:0, 0:0:0);
3186 $setuphold(posedge WCLK, posedge WDATA_13, 0:0:0, 0:0:0);
3187 $setuphold(posedge WCLK, negedge WDATA_13, 0:0:0, 0:0:0);
3188 $setuphold(negedge WCLK, posedge WDATA_13, 0:0:0, 0:0:0);
3189 $setuphold(negedge WCLK, negedge WDATA_13, 0:0:0, 0:0:0);
3190 $setuphold(posedge WCLK, posedge WDATA_12, 0:0:0, 0:0:0);
3191 $setuphold(posedge WCLK, negedge WDATA_12, 0:0:0, 0:0:0);
3192 $setuphold(negedge WCLK, posedge WDATA_12, 0:0:0, 0:0:0);
3193 $setuphold(negedge WCLK, negedge WDATA_12, 0:0:0, 0:0:0);
3194 $setuphold(posedge WCLK, posedge WDATA_11, 0:0:0, 0:0:0);
3195 $setuphold(posedge WCLK, negedge WDATA_11, 0:0:0, 0:0:0);
3196 $setuphold(negedge WCLK, posedge WDATA_11, 0:0:0, 0:0:0);
3197 $setuphold(negedge WCLK, negedge WDATA_11, 0:0:0, 0:0:0);
3198 $setuphold(posedge WCLK, posedge WDATA_10, 0:0:0, 0:0:0);
3199 $setuphold(posedge WCLK, negedge WDATA_10, 0:0:0, 0:0:0);
3200 $setuphold(negedge WCLK, posedge WDATA_10, 0:0:0, 0:0:0);
3201 $setuphold(negedge WCLK, negedge WDATA_10, 0:0:0, 0:0:0);
3202 $setuphold(posedge WCLK, posedge WDATA_9, 0:0:0, 0:0:0);
3203 $setuphold(posedge WCLK, negedge WDATA_9, 0:0:0, 0:0:0);
3204 $setuphold(negedge WCLK, posedge WDATA_9, 0:0:0, 0:0:0);
3205 $setuphold(negedge WCLK, negedge WDATA_9, 0:0:0, 0:0:0);
3206 $setuphold(posedge WCLK, posedge WDATA_8, 0:0:0, 0:0:0);
3207 $setuphold(posedge WCLK, negedge WDATA_8, 0:0:0, 0:0:0);
3208 $setuphold(negedge WCLK, posedge WDATA_8, 0:0:0, 0:0:0);
3209 $setuphold(negedge WCLK, negedge WDATA_8, 0:0:0, 0:0:0);
3210 $setuphold(posedge WCLK, posedge WDATA_7, 0:0:0, 0:0:0);
3211 $setuphold(posedge WCLK, negedge WDATA_7, 0:0:0, 0:0:0);
3212 $setuphold(negedge WCLK, posedge WDATA_7, 0:0:0, 0:0:0);
3213 $setuphold(negedge WCLK, negedge WDATA_7, 0:0:0, 0:0:0);
3214 $setuphold(posedge WCLK, posedge WDATA_6, 0:0:0, 0:0:0);
3215 $setuphold(posedge WCLK, negedge WDATA_6, 0:0:0, 0:0:0);
3216 $setuphold(negedge WCLK, posedge WDATA_6, 0:0:0, 0:0:0);
3217 $setuphold(negedge WCLK, negedge WDATA_6, 0:0:0, 0:0:0);
3218 $setuphold(posedge WCLK, posedge WDATA_5, 0:0:0, 0:0:0);
3219 $setuphold(posedge WCLK, negedge WDATA_5, 0:0:0, 0:0:0);
3220 $setuphold(negedge WCLK, posedge WDATA_5, 0:0:0, 0:0:0);
3221 $setuphold(negedge WCLK, negedge WDATA_5, 0:0:0, 0:0:0);
3222 $setuphold(posedge WCLK, posedge WDATA_4, 0:0:0, 0:0:0);
3223 $setuphold(posedge WCLK, negedge WDATA_4, 0:0:0, 0:0:0);
3224 $setuphold(negedge WCLK, posedge WDATA_4, 0:0:0, 0:0:0);
3225 $setuphold(negedge WCLK, negedge WDATA_4, 0:0:0, 0:0:0);
3226 $setuphold(posedge WCLK, posedge WDATA_3, 0:0:0, 0:0:0);
3227 $setuphold(posedge WCLK, negedge WDATA_3, 0:0:0, 0:0:0);
3228 $setuphold(negedge WCLK, posedge WDATA_3, 0:0:0, 0:0:0);
3229 $setuphold(negedge WCLK, negedge WDATA_3, 0:0:0, 0:0:0);
3230 $setuphold(posedge WCLK, posedge WDATA_2, 0:0:0, 0:0:0);
3231 $setuphold(posedge WCLK, negedge WDATA_2, 0:0:0, 0:0:0);
3232 $setuphold(negedge WCLK, posedge WDATA_2, 0:0:0, 0:0:0);
3233 $setuphold(negedge WCLK, negedge WDATA_2, 0:0:0, 0:0:0);
3234 $setuphold(posedge WCLK, posedge WDATA_1, 0:0:0, 0:0:0);
3235 $setuphold(posedge WCLK, negedge WDATA_1, 0:0:0, 0:0:0);
3236 $setuphold(negedge WCLK, posedge WDATA_1, 0:0:0, 0:0:0);
3237 $setuphold(negedge WCLK, negedge WDATA_1, 0:0:0, 0:0:0);
3238 $setuphold(posedge WCLK, posedge WDATA_0, 0:0:0, 0:0:0);
3239 $setuphold(posedge WCLK, negedge WDATA_0, 0:0:0, 0:0:0);
3240 $setuphold(negedge WCLK, posedge WDATA_0, 0:0:0, 0:0:0);
3241 $setuphold(negedge WCLK, negedge WDATA_0, 0:0:0, 0:0:0);
3242
3243 endspecify
3244 `endif
3245 endmodule