2 `define SB_DFF_REG reg Q = 0
3 // `define SB_DFF_REG reg Q
5 // SiliconBlue IO Cells
9 input LATCH_INPUT_VALUE,
19 parameter [5:0] PIN_TYPE = 6'b000000;
20 parameter [0:0] PULLUP = 1'b0;
21 parameter [0:0] NEG_TRIGGER = 1'b0;
22 parameter IO_STANDARD = "SB_LVCMOS";
25 reg dout, din_0, din_1;
27 reg dout_q_0, dout_q_1;
30 // IO tile generates a constant 1'b1 internally if global_cen is not connected
31 wire clken_pulled = CLOCK_ENABLE || CLOCK_ENABLE === 1'bz;
35 generate if (!NEG_TRIGGER) begin
36 always @(posedge INPUT_CLK) clken_pulled_ri <= clken_pulled;
37 always @(posedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN;
38 always @(negedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN;
39 always @(posedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled;
40 always @(posedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0;
41 always @(negedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1;
42 always @(posedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE;
44 always @(negedge INPUT_CLK) clken_pulled_ri <= clken_pulled;
45 always @(negedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN;
46 always @(posedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN;
47 always @(negedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled;
48 always @(negedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0;
49 always @(posedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1;
50 always @(negedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE;
54 if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
55 din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
59 // work around simulation glitches on dout in DDR mode
62 always @* outclk_delayed_1 <= OUTPUT_CLK;
63 always @* outclk_delayed_2 <= outclk_delayed_1;
67 dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
69 dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
72 assign D_IN_0 = din_0, D_IN_1 = din_1;
75 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
76 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
77 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
84 output GLOBAL_BUFFER_OUTPUT,
85 input LATCH_INPUT_VALUE,
95 parameter [5:0] PIN_TYPE = 6'b000000;
96 parameter [0:0] PULLUP = 1'b0;
97 parameter [0:0] NEG_TRIGGER = 1'b0;
98 parameter IO_STANDARD = "SB_LVCMOS";
100 assign GLOBAL_BUFFER_OUTPUT = PACKAGE_PIN;
105 .NEG_TRIGGER(NEG_TRIGGER),
106 .IO_STANDARD(IO_STANDARD)
108 .PACKAGE_PIN(PACKAGE_PIN),
109 .LATCH_INPUT_VALUE(LATCH_INPUT_VALUE),
110 .CLOCK_ENABLE(CLOCK_ENABLE),
111 .INPUT_CLK(INPUT_CLK),
112 .OUTPUT_CLK(OUTPUT_CLK),
113 .OUTPUT_ENABLE(OUTPUT_ENABLE),
122 input USER_SIGNAL_TO_GLOBAL_BUFFER,
123 output GLOBAL_BUFFER_OUTPUT
125 assign GLOBAL_BUFFER_OUTPUT = USER_SIGNAL_TO_GLOBAL_BUFFER;
128 // SiliconBlue Logic Cells
131 module SB_LUT4 (output O, input I0, I1, I2, I3);
132 parameter [15:0] LUT_INIT = 0;
133 wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
134 wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
135 wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];
136 assign O = I0 ? s1[1] : s1[0];
140 module SB_CARRY (output CO, input I0, I1, CI);
141 assign CO = (I0 && I1) || ((I0 || I1) && CI);
144 (* abc_box_id = 1, lib_whitebox *)
145 module \$__ICE40_FULL_ADDER (
146 (* abc_carry_out *) output CO,
150 (* abc_carry_in *) input CI
159 // I0: 1010 1010 1010 1010
160 // I1: 1100 1100 1100 1100
161 // I2: 1111 0000 1111 0000
162 // I3: 1111 1111 0000 0000
163 .LUT_INIT(16'b 0110_1001_1001_0110)
173 // Positive Edge SiliconBlue FF Cells
175 module SB_DFF (output `SB_DFF_REG, input C, D);
180 module SB_DFFE (output `SB_DFF_REG, input C, E, D);
186 module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
194 module SB_DFFR (output `SB_DFF_REG, input C, R, D);
195 always @(posedge C, posedge R)
202 module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
210 module SB_DFFS (output `SB_DFF_REG, input C, S, D);
211 always @(posedge C, posedge S)
218 module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
228 module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
229 always @(posedge C, posedge R)
236 module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
246 module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
247 always @(posedge C, posedge S)
254 // Negative Edge SiliconBlue FF Cells
256 module SB_DFFN (output `SB_DFF_REG, input C, D);
261 module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
267 module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
275 module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
276 always @(negedge C, posedge R)
283 module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
291 module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
292 always @(negedge C, posedge S)
299 module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
309 module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
310 always @(negedge C, posedge R)
317 module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
327 module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
328 always @(negedge C, posedge S)
335 // SiliconBlue RAM Cells
339 input RCLK, RCLKE, RE,
341 input WCLK, WCLKE, WE,
343 input [15:0] MASK, WDATA
349 parameter WRITE_MODE = 0;
350 parameter READ_MODE = 0;
352 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
353 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
354 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
355 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
356 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
357 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
358 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
359 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
360 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
361 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
362 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
363 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
364 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
365 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
366 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
367 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
369 parameter INIT_FILE = "";
380 0: assign WMASK_I = MASK;
382 1: assign WMASK_I = WADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
383 WADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
385 2: assign WMASK_I = WADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
386 WADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
387 WADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
388 WADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
390 3: assign WMASK_I = WADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
391 WADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
392 WADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
393 WADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
394 WADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
395 WADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
396 WADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
397 WADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
401 0: assign RMASK_I = 16'b 0000_0000_0000_0000;
403 1: assign RMASK_I = RADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
404 RADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
406 2: assign RMASK_I = RADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
407 RADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
408 RADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
409 RADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
411 3: assign RMASK_I = RADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
412 RADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
413 RADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
414 RADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
415 RADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
416 RADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
417 RADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
418 RADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
422 0: assign WDATA_I = WDATA;
424 1: assign WDATA_I = {WDATA[14], WDATA[14], WDATA[12], WDATA[12],
425 WDATA[10], WDATA[10], WDATA[ 8], WDATA[ 8],
426 WDATA[ 6], WDATA[ 6], WDATA[ 4], WDATA[ 4],
427 WDATA[ 2], WDATA[ 2], WDATA[ 0], WDATA[ 0]};
429 2: assign WDATA_I = {WDATA[13], WDATA[13], WDATA[13], WDATA[13],
430 WDATA[ 9], WDATA[ 9], WDATA[ 9], WDATA[ 9],
431 WDATA[ 5], WDATA[ 5], WDATA[ 5], WDATA[ 5],
432 WDATA[ 1], WDATA[ 1], WDATA[ 1], WDATA[ 1]};
434 3: assign WDATA_I = {WDATA[11], WDATA[11], WDATA[11], WDATA[11],
435 WDATA[11], WDATA[11], WDATA[11], WDATA[11],
436 WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3],
437 WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3]};
441 0: assign RDATA = RDATA_I;
442 1: assign RDATA = {1'b0, |RDATA_I[15:14], 1'b0, |RDATA_I[13:12], 1'b0, |RDATA_I[11:10], 1'b0, |RDATA_I[ 9: 8],
443 1'b0, |RDATA_I[ 7: 6], 1'b0, |RDATA_I[ 5: 4], 1'b0, |RDATA_I[ 3: 2], 1'b0, |RDATA_I[ 1: 0]};
444 2: assign RDATA = {2'b0, |RDATA_I[15:12], 3'b0, |RDATA_I[11: 8], 3'b0, |RDATA_I[ 7: 4], 3'b0, |RDATA_I[ 3: 0], 1'b0};
445 3: assign RDATA = {4'b0, |RDATA_I[15: 8], 7'b0, |RDATA_I[ 7: 0], 3'b0};
450 reg [15:0] memory [0:255];
454 $readmemh(INIT_FILE, memory);
456 for (i=0; i<16; i=i+1) begin
457 memory[ 0*16 + i] = INIT_0[16*i +: 16];
458 memory[ 1*16 + i] = INIT_1[16*i +: 16];
459 memory[ 2*16 + i] = INIT_2[16*i +: 16];
460 memory[ 3*16 + i] = INIT_3[16*i +: 16];
461 memory[ 4*16 + i] = INIT_4[16*i +: 16];
462 memory[ 5*16 + i] = INIT_5[16*i +: 16];
463 memory[ 6*16 + i] = INIT_6[16*i +: 16];
464 memory[ 7*16 + i] = INIT_7[16*i +: 16];
465 memory[ 8*16 + i] = INIT_8[16*i +: 16];
466 memory[ 9*16 + i] = INIT_9[16*i +: 16];
467 memory[10*16 + i] = INIT_A[16*i +: 16];
468 memory[11*16 + i] = INIT_B[16*i +: 16];
469 memory[12*16 + i] = INIT_C[16*i +: 16];
470 memory[13*16 + i] = INIT_D[16*i +: 16];
471 memory[14*16 + i] = INIT_E[16*i +: 16];
472 memory[15*16 + i] = INIT_F[16*i +: 16];
476 always @(posedge WCLK) begin
477 if (WE && WCLKE) begin
478 if (!WMASK_I[ 0]) memory[WADDR[7:0]][ 0] <= WDATA_I[ 0];
479 if (!WMASK_I[ 1]) memory[WADDR[7:0]][ 1] <= WDATA_I[ 1];
480 if (!WMASK_I[ 2]) memory[WADDR[7:0]][ 2] <= WDATA_I[ 2];
481 if (!WMASK_I[ 3]) memory[WADDR[7:0]][ 3] <= WDATA_I[ 3];
482 if (!WMASK_I[ 4]) memory[WADDR[7:0]][ 4] <= WDATA_I[ 4];
483 if (!WMASK_I[ 5]) memory[WADDR[7:0]][ 5] <= WDATA_I[ 5];
484 if (!WMASK_I[ 6]) memory[WADDR[7:0]][ 6] <= WDATA_I[ 6];
485 if (!WMASK_I[ 7]) memory[WADDR[7:0]][ 7] <= WDATA_I[ 7];
486 if (!WMASK_I[ 8]) memory[WADDR[7:0]][ 8] <= WDATA_I[ 8];
487 if (!WMASK_I[ 9]) memory[WADDR[7:0]][ 9] <= WDATA_I[ 9];
488 if (!WMASK_I[10]) memory[WADDR[7:0]][10] <= WDATA_I[10];
489 if (!WMASK_I[11]) memory[WADDR[7:0]][11] <= WDATA_I[11];
490 if (!WMASK_I[12]) memory[WADDR[7:0]][12] <= WDATA_I[12];
491 if (!WMASK_I[13]) memory[WADDR[7:0]][13] <= WDATA_I[13];
492 if (!WMASK_I[14]) memory[WADDR[7:0]][14] <= WDATA_I[14];
493 if (!WMASK_I[15]) memory[WADDR[7:0]][15] <= WDATA_I[15];
497 always @(posedge RCLK) begin
498 if (RE && RCLKE) begin
499 RDATA_I <= memory[RADDR[7:0]] & ~RMASK_I;
505 module SB_RAM40_4KNR (
507 input RCLKN, RCLKE, RE,
509 input WCLK, WCLKE, WE,
511 input [15:0] MASK, WDATA
513 parameter WRITE_MODE = 0;
514 parameter READ_MODE = 0;
516 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
517 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
518 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
519 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
520 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
521 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
522 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
523 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
524 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
525 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
526 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
527 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
528 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
529 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
530 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
531 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
533 parameter INIT_FILE = "";
536 .WRITE_MODE(WRITE_MODE),
537 .READ_MODE (READ_MODE ),
554 .INIT_FILE (INIT_FILE )
570 module SB_RAM40_4KNW (
572 input RCLK, RCLKE, RE,
574 input WCLKN, WCLKE, WE,
576 input [15:0] MASK, WDATA
578 parameter WRITE_MODE = 0;
579 parameter READ_MODE = 0;
581 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
582 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
583 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
584 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
585 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
586 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
587 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
588 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
589 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
590 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
591 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
592 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
593 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
594 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
595 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
596 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
598 parameter INIT_FILE = "";
601 .WRITE_MODE(WRITE_MODE),
602 .READ_MODE (READ_MODE ),
619 .INIT_FILE (INIT_FILE )
635 module SB_RAM40_4KNRNW (
637 input RCLKN, RCLKE, RE,
639 input WCLKN, WCLKE, WE,
641 input [15:0] MASK, WDATA
643 parameter WRITE_MODE = 0;
644 parameter READ_MODE = 0;
646 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
647 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
648 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
649 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
650 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
651 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
652 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
653 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
654 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
655 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
656 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
657 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
658 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
659 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
660 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
661 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
663 parameter INIT_FILE = "";
666 .WRITE_MODE(WRITE_MODE),
667 .READ_MODE (READ_MODE ),
684 .INIT_FILE (INIT_FILE )
700 // Packed IceStorm Logic Cells
703 input I0, I1, I2, I3, CIN, CLK, CEN, SR,
706 parameter [15:0] LUT_INIT = 0;
708 parameter [0:0] NEG_CLK = 0;
709 parameter [0:0] CARRY_ENABLE = 0;
710 parameter [0:0] DFF_ENABLE = 0;
711 parameter [0:0] SET_NORESET = 0;
712 parameter [0:0] ASYNC_SR = 0;
714 parameter [0:0] CIN_CONST = 0;
715 parameter [0:0] CIN_SET = 0;
717 wire mux_cin = CIN_CONST ? CIN_SET : CIN;
719 assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && mux_cin) : 1'bx;
721 wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
722 wire [3:0] lut_s2 = I2 ? lut_s3[ 7:4] : lut_s3[3:0];
723 wire [1:0] lut_s1 = I1 ? lut_s2[ 3:2] : lut_s2[1:0];
724 wire lut_o = I0 ? lut_s1[ 1] : lut_s1[ 0];
729 assign polarized_clk = CLK ^ NEG_CLK;
732 always @(posedge polarized_clk)
734 o_reg <= SR ? SET_NORESET : lut_o;
737 always @(posedge polarized_clk, posedge SR)
739 o_reg <= SET_NORESET;
743 assign O = DFF_ENABLE ? ASYNC_SR ? o_reg_async : o_reg : lut_o;
746 // SiliconBlue PLL Cells
749 module SB_PLL40_CORE (
754 input [7:0] DYNAMICDELAY,
758 input LATCHINPUTVALUE,
763 parameter FEEDBACK_PATH = "SIMPLE";
764 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
765 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
766 parameter SHIFTREG_DIV_MODE = 1'b0;
767 parameter FDA_FEEDBACK = 4'b0000;
768 parameter FDA_RELATIVE = 4'b0000;
769 parameter PLLOUT_SELECT = "GENCLK";
770 parameter DIVR = 4'b0000;
771 parameter DIVF = 7'b0000000;
772 parameter DIVQ = 3'b000;
773 parameter FILTER_RANGE = 3'b000;
774 parameter ENABLE_ICEGATE = 1'b0;
775 parameter TEST_MODE = 1'b0;
776 parameter EXTERNAL_DIVIDE_FACTOR = 1;
780 module SB_PLL40_PAD (
785 input [7:0] DYNAMICDELAY,
789 input LATCHINPUTVALUE,
794 parameter FEEDBACK_PATH = "SIMPLE";
795 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
796 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
797 parameter SHIFTREG_DIV_MODE = 1'b0;
798 parameter FDA_FEEDBACK = 4'b0000;
799 parameter FDA_RELATIVE = 4'b0000;
800 parameter PLLOUT_SELECT = "GENCLK";
801 parameter DIVR = 4'b0000;
802 parameter DIVF = 7'b0000000;
803 parameter DIVQ = 3'b000;
804 parameter FILTER_RANGE = 3'b000;
805 parameter ENABLE_ICEGATE = 1'b0;
806 parameter TEST_MODE = 1'b0;
807 parameter EXTERNAL_DIVIDE_FACTOR = 1;
811 module SB_PLL40_2_PAD (
814 output PLLOUTGLOBALA,
816 output PLLOUTGLOBALB,
818 input [7:0] DYNAMICDELAY,
822 input LATCHINPUTVALUE,
827 parameter FEEDBACK_PATH = "SIMPLE";
828 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
829 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
830 parameter SHIFTREG_DIV_MODE = 1'b0;
831 parameter FDA_FEEDBACK = 4'b0000;
832 parameter FDA_RELATIVE = 4'b0000;
833 parameter PLLOUT_SELECT_PORTB = "GENCLK";
834 parameter DIVR = 4'b0000;
835 parameter DIVF = 7'b0000000;
836 parameter DIVQ = 3'b000;
837 parameter FILTER_RANGE = 3'b000;
838 parameter ENABLE_ICEGATE_PORTA = 1'b0;
839 parameter ENABLE_ICEGATE_PORTB = 1'b0;
840 parameter TEST_MODE = 1'b0;
841 parameter EXTERNAL_DIVIDE_FACTOR = 1;
845 module SB_PLL40_2F_CORE (
848 output PLLOUTGLOBALA,
850 output PLLOUTGLOBALB,
852 input [7:0] DYNAMICDELAY,
856 input LATCHINPUTVALUE,
861 parameter FEEDBACK_PATH = "SIMPLE";
862 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
863 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
864 parameter SHIFTREG_DIV_MODE = 1'b0;
865 parameter FDA_FEEDBACK = 4'b0000;
866 parameter FDA_RELATIVE = 4'b0000;
867 parameter PLLOUT_SELECT_PORTA = "GENCLK";
868 parameter PLLOUT_SELECT_PORTB = "GENCLK";
869 parameter DIVR = 4'b0000;
870 parameter DIVF = 7'b0000000;
871 parameter DIVQ = 3'b000;
872 parameter FILTER_RANGE = 3'b000;
873 parameter ENABLE_ICEGATE_PORTA = 1'b0;
874 parameter ENABLE_ICEGATE_PORTB = 1'b0;
875 parameter TEST_MODE = 1'b0;
876 parameter EXTERNAL_DIVIDE_FACTOR = 1;
880 module SB_PLL40_2F_PAD (
883 output PLLOUTGLOBALA,
885 output PLLOUTGLOBALB,
887 input [7:0] DYNAMICDELAY,
891 input LATCHINPUTVALUE,
896 parameter FEEDBACK_PATH = "SIMPLE";
897 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
898 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
899 parameter SHIFTREG_DIV_MODE = 2'b00;
900 parameter FDA_FEEDBACK = 4'b0000;
901 parameter FDA_RELATIVE = 4'b0000;
902 parameter PLLOUT_SELECT_PORTA = "GENCLK";
903 parameter PLLOUT_SELECT_PORTB = "GENCLK";
904 parameter DIVR = 4'b0000;
905 parameter DIVF = 7'b0000000;
906 parameter DIVQ = 3'b000;
907 parameter FILTER_RANGE = 3'b000;
908 parameter ENABLE_ICEGATE_PORTA = 1'b0;
909 parameter ENABLE_ICEGATE_PORTB = 1'b0;
910 parameter TEST_MODE = 1'b0;
911 parameter EXTERNAL_DIVIDE_FACTOR = 1;
914 // SiliconBlue Device Configuration Cells
924 module SB_SPRAM256KA (
925 input [13:0] ADDRESS,
927 input [3:0] MASKWREN,
928 input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
929 output reg [15:0] DATAOUT
933 reg [15:0] mem [0:16383];
934 wire off = SLEEP || !POWEROFF;
937 always @(negedge POWEROFF) begin
938 for (i = 0; i <= 16383; i = i+1)
942 always @(posedge CLOCK, posedge off) begin
946 if (CHIPSELECT && !STANDBY && !WREN) begin
947 DATAOUT <= mem[ADDRESS];
949 if (CHIPSELECT && !STANDBY && WREN) begin
950 if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0];
951 if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4];
952 if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8];
953 if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12];
978 parameter TRIM_EN = "0b0";
979 parameter CLKHF_DIV = "0b00";
1001 parameter CURRENT_MODE = "0b0";
1002 parameter RGB0_CURRENT = "0b000000";
1003 parameter RGB1_CURRENT = "0b000000";
1004 parameter RGB2_CURRENT = "0b000000";
1008 module SB_LED_DRV_CUR(
1025 parameter CURRENT_MODE = "0b0";
1026 parameter RGB0_CURRENT = "0b000000";
1027 parameter RGB1_CURRENT = "0b000000";
1028 parameter RGB2_CURRENT = "0b000000";
1065 output SCLO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
1070 parameter I2C_SLAVE_INIT_ADDR = "0b1111100001";
1071 parameter BUS_ADDR74 = "0b0001";
1114 output SCKO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
1125 parameter BUS_ADDR74 = "0b0000";
1155 module SB_FILTER_50NS(
1163 input LATCH_INPUT_VALUE,
1167 input OUTPUT_ENABLE,
1175 parameter [5:0] PIN_TYPE = 6'b000000;
1176 parameter [0:0] PULLUP = 1'b0;
1177 parameter [0:0] WEAK_PULLUP = 1'b0;
1178 parameter [0:0] NEG_TRIGGER = 1'b0;
1179 parameter IO_STANDARD = "SB_LVCMOS";
1182 reg dout, din_0, din_1;
1183 reg din_q_0, din_q_1;
1184 reg dout_q_0, dout_q_1;
1187 generate if (!NEG_TRIGGER) begin
1188 always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
1189 always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
1190 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
1191 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
1192 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
1194 always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
1195 always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
1196 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
1197 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
1198 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
1202 if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
1203 din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
1207 // work around simulation glitches on dout in DDR mode
1208 reg outclk_delayed_1;
1209 reg outclk_delayed_2;
1210 always @* outclk_delayed_1 <= OUTPUT_CLK;
1211 always @* outclk_delayed_2 <= outclk_delayed_1;
1215 dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
1217 dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
1220 assign D_IN_0 = din_0, D_IN_1 = din_1;
1223 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
1224 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
1225 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
1232 input LATCHINPUTVALUE,
1242 parameter [5:0] PIN_TYPE = 6'b000000;
1243 parameter [0:0] NEG_TRIGGER = 1'b0;
1246 reg dout, din_0, din_1;
1247 reg din_q_0, din_q_1;
1248 reg dout_q_0, dout_q_1;
1251 generate if (!NEG_TRIGGER) begin
1252 always @(posedge INPUTCLK) if (CLOCKENABLE) din_q_0 <= PACKAGEPIN;
1253 always @(negedge INPUTCLK) if (CLOCKENABLE) din_q_1 <= PACKAGEPIN;
1254 always @(posedge OUTPUTCLK) if (CLOCKENABLE) dout_q_0 <= DOUT0;
1255 always @(negedge OUTPUTCLK) if (CLOCKENABLE) dout_q_1 <= DOUT1;
1256 always @(posedge OUTPUTCLK) if (CLOCKENABLE) outena_q <= OUTPUTENABLE;
1258 always @(negedge INPUTCLK) if (CLOCKENABLE) din_q_0 <= PACKAGEPIN;
1259 always @(posedge INPUTCLK) if (CLOCKENABLE) din_q_1 <= PACKAGEPIN;
1260 always @(negedge OUTPUTCLK) if (CLOCKENABLE) dout_q_0 <= DOUT0;
1261 always @(posedge OUTPUTCLK) if (CLOCKENABLE) dout_q_1 <= DOUT1;
1262 always @(negedge OUTPUTCLK) if (CLOCKENABLE) outena_q <= OUTPUTENABLE;
1266 if (!PIN_TYPE[1] || !LATCHINPUTVALUE)
1267 din_0 = PIN_TYPE[0] ? PACKAGEPIN : din_q_0;
1271 // work around simulation glitches on dout in DDR mode
1272 reg outclk_delayed_1;
1273 reg outclk_delayed_2;
1274 always @* outclk_delayed_1 <= OUTPUTCLK;
1275 always @* outclk_delayed_2 <= outclk_delayed_1;
1279 dout = PIN_TYPE[2] ? !dout_q_0 : DOUT0;
1281 dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
1284 assign DIN0 = din_0, DIN1 = din_1;
1287 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGEPIN = dout ? 1'bz : 1'b0;
1288 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGEPIN = OUTPUTENABLE ? (dout ? 1'bz : 1'b0) : 1'bz;
1289 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGEPIN = outena_q ? (dout ? 1'bz : 1'b0) : 1'bz;
1296 input [15:0] C, A, B, D,
1297 input AHOLD, BHOLD, CHOLD, DHOLD,
1298 input IRSTTOP, IRSTBOT,
1299 input ORSTTOP, ORSTBOT,
1300 input OLOADTOP, OLOADBOT,
1301 input ADDSUBTOP, ADDSUBBOT,
1302 input OHOLDTOP, OHOLDBOT,
1303 input CI, ACCUMCI, SIGNEXTIN,
1305 output CO, ACCUMCO, SIGNEXTOUT
1307 parameter [0:0] NEG_TRIGGER = 0;
1308 parameter [0:0] C_REG = 0;
1309 parameter [0:0] A_REG = 0;
1310 parameter [0:0] B_REG = 0;
1311 parameter [0:0] D_REG = 0;
1312 parameter [0:0] TOP_8x8_MULT_REG = 0;
1313 parameter [0:0] BOT_8x8_MULT_REG = 0;
1314 parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
1315 parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
1316 parameter [1:0] TOPOUTPUT_SELECT = 0;
1317 parameter [1:0] TOPADDSUB_LOWERINPUT = 0;
1318 parameter [0:0] TOPADDSUB_UPPERINPUT = 0;
1319 parameter [1:0] TOPADDSUB_CARRYSELECT = 0;
1320 parameter [1:0] BOTOUTPUT_SELECT = 0;
1321 parameter [1:0] BOTADDSUB_LOWERINPUT = 0;
1322 parameter [0:0] BOTADDSUB_UPPERINPUT = 0;
1323 parameter [1:0] BOTADDSUB_CARRYSELECT = 0;
1324 parameter [0:0] MODE_8x8 = 0;
1325 parameter [0:0] A_SIGNED = 0;
1326 parameter [0:0] B_SIGNED = 0;
1328 wire clock = CLK ^ NEG_TRIGGER;
1330 // internal wires, compare Figure on page 133 of ICE Technology Library 3.0 and Fig 2 on page 2 of Lattice TN1295-DSP
1331 // http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201608.pdf
1332 // https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/AD/DSPFunctionUsageGuideforICE40Devices.ashx
1333 wire [15:0] iA, iB, iC, iD;
1334 wire [15:0] iF, iJ, iK, iG;
1336 wire [15:0] iW, iX, iP, iQ;
1337 wire [15:0] iY, iZ, iR, iS;
1342 always @(posedge clock, posedge IRSTTOP) begin
1346 end else if (CE) begin
1347 if (!CHOLD) rC <= C;
1348 if (!AHOLD) rA <= A;
1351 assign iC = C_REG ? rC : C;
1352 assign iA = A_REG ? rA : A;
1356 always @(posedge clock, posedge IRSTBOT) begin
1360 end else if (CE) begin
1361 if (!BHOLD) rB <= B;
1362 if (!DHOLD) rD <= D;
1365 assign iB = B_REG ? rB : B;
1366 assign iD = D_REG ? rD : D;
1369 wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
1370 wire [15:0] Ah, Al, Bh, Bl;
1371 assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]};
1372 assign Al = {A_SIGNED && MODE_8x8 ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
1373 assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]};
1374 assign Bl = {B_SIGNED && MODE_8x8 ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
1375 assign p_Ah_Bh = Ah * Bh; // F
1376 assign p_Al_Bh = {8'b0, Al[7:0]} * Bh; // J
1377 assign p_Ah_Bl = Ah * {8'b0, Bl[7:0]}; // K
1378 assign p_Al_Bl = Al * Bl; // G
1382 always @(posedge clock, posedge IRSTTOP) begin
1386 end else if (CE) begin
1388 if (!MODE_8x8) rJ <= p_Al_Bh;
1391 assign iF = TOP_8x8_MULT_REG ? rF : p_Ah_Bh;
1392 assign iJ = PIPELINE_16x16_MULT_REG1 ? rJ : p_Al_Bh;
1396 always @(posedge clock, posedge IRSTBOT) begin
1400 end else if (CE) begin
1401 if (!MODE_8x8) rK <= p_Ah_Bl;
1405 assign iK = PIPELINE_16x16_MULT_REG1 ? rK : p_Ah_Bl;
1406 assign iG = BOT_8x8_MULT_REG ? rG : p_Al_Bl;
1409 wire [23:0] iK_e = {A_SIGNED ? {8{iK[15]}} : 8'b0, iK};
1410 wire [23:0] iJ_e = {B_SIGNED ? {8{iJ[15]}} : 8'b0, iJ};
1411 assign iL = iG + (iK_e << 8) + (iJ_e << 8) + (iF << 16);
1415 always @(posedge clock, posedge IRSTBOT) begin
1418 end else if (CE) begin
1419 if (!MODE_8x8) rH <= iL;
1422 assign iH = PIPELINE_16x16_MULT_REG2 ? rH : iL;
1427 assign iW = TOPADDSUB_UPPERINPUT ? iC : iQ;
1428 assign iX = (TOPADDSUB_LOWERINPUT == 0) ? iA : (TOPADDSUB_LOWERINPUT == 1) ? iF : (TOPADDSUB_LOWERINPUT == 2) ? iH[31:16] : {16{iZ[15]}};
1429 assign {ACCUMCO, XW} = iX + (iW ^ {16{ADDSUBTOP}}) + HCI;
1430 assign CO = ACCUMCO ^ ADDSUBTOP;
1431 assign iP = OLOADTOP ? iC : XW ^ {16{ADDSUBTOP}};
1432 always @(posedge clock, posedge ORSTTOP) begin
1435 end else if (CE) begin
1436 if (!OHOLDTOP) rQ <= iP;
1440 assign Oh = (TOPOUTPUT_SELECT == 0) ? iP : (TOPOUTPUT_SELECT == 1) ? iQ : (TOPOUTPUT_SELECT == 2) ? iF : iH[31:16];
1441 assign HCI = (TOPADDSUB_CARRYSELECT == 0) ? 1'b0 : (TOPADDSUB_CARRYSELECT == 1) ? 1'b1 : (TOPADDSUB_CARRYSELECT == 2) ? LCO : LCO ^ ADDSUBBOT;
1442 assign SIGNEXTOUT = iX[15];
1447 assign iY = BOTADDSUB_UPPERINPUT ? iD : iS;
1448 assign iZ = (BOTADDSUB_LOWERINPUT == 0) ? iB : (BOTADDSUB_LOWERINPUT == 1) ? iG : (BOTADDSUB_LOWERINPUT == 2) ? iH[15:0] : {16{SIGNEXTIN}};
1449 assign {LCO, YZ} = iZ + (iY ^ {16{ADDSUBBOT}}) + LCI;
1450 assign iR = OLOADBOT ? iD : YZ ^ {16{ADDSUBBOT}};
1451 always @(posedge clock, posedge ORSTBOT) begin
1454 end else if (CE) begin
1455 if (!OHOLDBOT) rS <= iR;
1459 assign Ol = (BOTOUTPUT_SELECT == 0) ? iR : (BOTOUTPUT_SELECT == 1) ? iS : (BOTOUTPUT_SELECT == 2) ? iG : iH[15:0];
1460 assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI;
1461 assign O = {Oh, Ol};