techlibs/ice40/cells_sim.v

   1
   2 `define SB_DFF_REG reg Q = 0
   3 // `define SB_DFF_REG reg Q
   4
   5 // SiliconBlue IO Cells
   6
   7 module SB_IO (
   8         inout  PACKAGE_PIN,
   9         input  LATCH_INPUT_VALUE,
  10         input  CLOCK_ENABLE,
  11         input  INPUT_CLK,
  12         input  OUTPUT_CLK,
  13         input  OUTPUT_ENABLE,
  14         input  D_OUT_0,
  15         input  D_OUT_1,
  16         output D_IN_0,
  17         output D_IN_1
  18 );
  19         parameter [5:0] PIN_TYPE = 6'b000000;
  20         parameter [0:0] PULLUP = 1'b0;
  21         parameter [0:0] NEG_TRIGGER = 1'b0;
  22         parameter IO_STANDARD = "SB_LVCMOS";
  23
  24 `ifndef BLACKBOX
  25         reg dout, din_0, din_1;
  26         reg din_q_0, din_q_1;
  27         reg dout_q_0, dout_q_1;
  28         reg outena_q;
  29
  30         // IO tile generates a constant 1'b1 internally if global_cen is not connected
  31         wire clken_pulled = CLOCK_ENABLE || CLOCK_ENABLE === 1'bz;
  32         reg  clken_pulled_ri;
  33         reg  clken_pulled_ro;
  34
  35         generate if (!NEG_TRIGGER) begin
  36                 always @(posedge INPUT_CLK)                       clken_pulled_ri <= clken_pulled;
  37                 always @(posedge INPUT_CLK)  if (clken_pulled)    din_q_0         <= PACKAGE_PIN;
  38                 always @(negedge INPUT_CLK)  if (clken_pulled_ri) din_q_1         <= PACKAGE_PIN;
  39                 always @(posedge OUTPUT_CLK)                      clken_pulled_ro <= clken_pulled;
  40                 always @(posedge OUTPUT_CLK) if (clken_pulled)    dout_q_0        <= D_OUT_0;
  41                 always @(negedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1        <= D_OUT_1;
  42                 always @(posedge OUTPUT_CLK) if (clken_pulled)    outena_q        <= OUTPUT_ENABLE;
  43         end else begin
  44                 always @(negedge INPUT_CLK)                       clken_pulled_ri <= clken_pulled;
  45                 always @(negedge INPUT_CLK)  if (clken_pulled)    din_q_0         <= PACKAGE_PIN;
  46                 always @(posedge INPUT_CLK)  if (clken_pulled_ri) din_q_1         <= PACKAGE_PIN;
  47                 always @(negedge OUTPUT_CLK)                      clken_pulled_ro <= clken_pulled;
  48                 always @(negedge OUTPUT_CLK) if (clken_pulled)    dout_q_0        <= D_OUT_0;
  49                 always @(posedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1        <= D_OUT_1;
  50                 always @(negedge OUTPUT_CLK) if (clken_pulled)    outena_q        <= OUTPUT_ENABLE;
  51         end endgenerate
  52
  53         always @* begin
  54                 if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
  55                         din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
  56                 din_1 = din_q_1;
  57         end
  58
  59         // work around simulation glitches on dout in DDR mode
  60         reg outclk_delayed_1;
  61         reg outclk_delayed_2;
  62         always @* outclk_delayed_1 <= OUTPUT_CLK;
  63         always @* outclk_delayed_2 <= outclk_delayed_1;
  64
  65         always @* begin
  66                 if (PIN_TYPE[3])
  67                         dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
  68                 else
  69                         dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
  70         end
  71
  72         assign D_IN_0 = din_0, D_IN_1 = din_1;
  73
  74         generate
  75                 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
  76                 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
  77                 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
  78         endgenerate
  79 `endif
  80 endmodule
  81
  82 module SB_GB_IO (
  83         inout  PACKAGE_PIN,
  84         output GLOBAL_BUFFER_OUTPUT,
  85         input  LATCH_INPUT_VALUE,
  86         input  CLOCK_ENABLE,
  87         input  INPUT_CLK,
  88         input  OUTPUT_CLK,
  89         input  OUTPUT_ENABLE,
  90         input  D_OUT_0,
  91         input  D_OUT_1,
  92         output D_IN_0,
  93         output D_IN_1
  94 );
  95         parameter [5:0] PIN_TYPE = 6'b000000;
  96         parameter [0:0] PULLUP = 1'b0;
  97         parameter [0:0] NEG_TRIGGER = 1'b0;
  98         parameter IO_STANDARD = "SB_LVCMOS";
  99
 100         assign GLOBAL_BUFFER_OUTPUT = PACKAGE_PIN;
 101
 102         SB_IO #(
 103                 .PIN_TYPE(PIN_TYPE),
 104                 .PULLUP(PULLUP),
 105                 .NEG_TRIGGER(NEG_TRIGGER),
 106                 .IO_STANDARD(IO_STANDARD)
 107         ) IO (
 108                 .PACKAGE_PIN(PACKAGE_PIN),
 109                 .LATCH_INPUT_VALUE(LATCH_INPUT_VALUE),
 110                 .CLOCK_ENABLE(CLOCK_ENABLE),
 111                 .INPUT_CLK(INPUT_CLK),
 112                 .OUTPUT_CLK(OUTPUT_CLK),
 113                 .OUTPUT_ENABLE(OUTPUT_ENABLE),
 114                 .D_OUT_0(D_OUT_0),
 115                 .D_OUT_1(D_OUT_1),
 116                 .D_IN_0(D_IN_0),
 117                 .D_IN_1(D_IN_1)
 118         );
 119 endmodule
 120
 121 module SB_GB (
 122         input  USER_SIGNAL_TO_GLOBAL_BUFFER,
 123         output GLOBAL_BUFFER_OUTPUT
 124 );
 125         assign GLOBAL_BUFFER_OUTPUT = USER_SIGNAL_TO_GLOBAL_BUFFER;
 126 endmodule
 127
 128 // SiliconBlue Logic Cells
 129
 130 (* abc_box_id = 22, lib_whitebox *)
 131 module SB_LUT4 (output O, input I0, I1, I2, I3);
 132         parameter [15:0] LUT_INIT = 0;
 133         wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
 134         wire [3:0] s2 = I2 ?       s3[ 7:4] :       s3[3:0];
 135         wire [1:0] s1 = I1 ?       s2[ 3:2] :       s2[1:0];
 136         assign O = I0 ? s1[1] : s1[0];
 137 endmodule
 138
 139 (* abc_box_id = 21, abc_carry, lib_whitebox *)
 140 module SB_CARRY ((* abc_carry_out *) output CO, input I0, I1, (* abc_carry_in *) input CI);
 141         assign CO = (I0 && I1) || ((I0 || I1) && CI);
 142 endmodule
 143
 144 // Positive Edge SiliconBlue FF Cells
 145
 146 module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
 147 `ifndef _ABC
 148         always @(posedge C)
 149                 Q <= D;
 150 `else
 151     always @* Q <= D;
 152 `endif
 153 endmodule
 154
 155 module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
 156         always @(posedge C)
 157                 if (E)
 158                         Q <= D;
 159 endmodule
 160
 161 module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 162         always @(posedge C)
 163                 if (R)
 164                         Q <= 0;
 165                 else
 166                         Q <= D;
 167 endmodule
 168
 169 module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 170         always @(posedge C, posedge R)
 171                 if (R)
 172                         Q <= 0;
 173                 else
 174                         Q <= D;
 175 endmodule
 176
 177 module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 178         always @(posedge C)
 179                 if (S)
 180                         Q <= 1;
 181                 else
 182                         Q <= D;
 183 endmodule
 184
 185 module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 186         always @(posedge C, posedge S)
 187                 if (S)
 188                         Q <= 1;
 189                 else
 190                         Q <= D;
 191 endmodule
 192
 193 module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 194         always @(posedge C)
 195                 if (E) begin
 196                         if (R)
 197                                 Q <= 0;
 198                         else
 199                                 Q <= D;
 200                 end
 201 endmodule
 202
 203 module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 204         always @(posedge C, posedge R)
 205                 if (R)
 206                         Q <= 0;
 207                 else if (E)
 208                         Q <= D;
 209 endmodule
 210
 211 module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 212         always @(posedge C)
 213                 if (E) begin
 214                         if (S)
 215                                 Q <= 1;
 216                         else
 217                                 Q <= D;
 218                 end
 219 endmodule
 220
 221 module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 222         always @(posedge C, posedge S)
 223                 if (S)
 224                         Q <= 1;
 225                 else if (E)
 226                         Q <= D;
 227 endmodule
 228
 229 // Negative Edge SiliconBlue FF Cells
 230
 231 module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, D);
 232         always @(negedge C)
 233                 Q <= D;
 234 endmodule
 235
 236 module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, D);
 237         always @(negedge C)
 238                 if (E)
 239                         Q <= D;
 240 endmodule
 241
 242 module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 243         always @(negedge C)
 244                 if (R)
 245                         Q <= 0;
 246                 else
 247                         Q <= D;
 248 endmodule
 249
 250 module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, D);
 251         always @(negedge C, posedge R)
 252                 if (R)
 253                         Q <= 0;
 254                 else
 255                         Q <= D;
 256 endmodule
 257
 258 module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 259         always @(negedge C)
 260                 if (S)
 261                         Q <= 1;
 262                 else
 263                         Q <= D;
 264 endmodule
 265
 266 module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, D);
 267         always @(negedge C, posedge S)
 268                 if (S)
 269                         Q <= 1;
 270                 else
 271                         Q <= D;
 272 endmodule
 273
 274 module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 275         always @(negedge C)
 276                 if (E) begin
 277                         if (R)
 278                                 Q <= 0;
 279                         else
 280                                 Q <= D;
 281                 end
 282 endmodule
 283
 284 module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, D);
 285         always @(negedge C, posedge R)
 286                 if (R)
 287                         Q <= 0;
 288                 else if (E)
 289                         Q <= D;
 290 endmodule
 291
 292 module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 293         always @(negedge C)
 294                 if (E) begin
 295                         if (S)
 296                                 Q <= 1;
 297                         else
 298                                 Q <= D;
 299                 end
 300 endmodule
 301
 302 module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, D);
 303         always @(negedge C, posedge S)
 304                 if (S)
 305                         Q <= 1;
 306                 else if (E)
 307                         Q <= D;
 308 endmodule
 309
 310 // SiliconBlue RAM Cells
 311
 312 module SB_RAM40_4K (
 313         (* abc_flop_q *) output [15:0] RDATA,
 314         input         RCLK, RCLKE, RE,
 315         input  [10:0] RADDR,
 316         input         WCLK, WCLKE, WE,
 317         input  [10:0] WADDR,
 318         input  [15:0] MASK, WDATA
 319 );
 320         // MODE 0:  256 x 16
 321         // MODE 1:  512 x 8
 322         // MODE 2: 1024 x 4
 323         // MODE 3: 2048 x 2
 324         parameter WRITE_MODE = 0;
 325         parameter READ_MODE = 0;
 326
 327         parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 328         parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 329         parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 330         parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 331         parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 332         parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 333         parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 334         parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 335         parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 336         parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 337         parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 338         parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 339         parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 340         parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 341         parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 342         parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 343
 344         parameter INIT_FILE = "";
 345
 346 `ifndef BLACKBOX
 347         wire [15:0] WMASK_I;
 348         wire [15:0] RMASK_I;
 349
 350         reg  [15:0] RDATA_I;
 351         wire [15:0] WDATA_I;
 352
 353         generate
 354                 case (WRITE_MODE)
 355                         0: assign WMASK_I = MASK;
 356
 357                         1: assign WMASK_I = WADDR[   8] == 0 ? 16'b 1010_1010_1010_1010 :
 358                                             WADDR[   8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
 359
 360                         2: assign WMASK_I = WADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
 361                                             WADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
 362                                             WADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
 363                                             WADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
 364
 365                         3: assign WMASK_I = WADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
 366                                             WADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
 367                                             WADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
 368                                             WADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
 369                                             WADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
 370                                             WADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
 371                                             WADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
 372                                             WADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
 373                 endcase
 374
 375                 case (READ_MODE)
 376                         0: assign RMASK_I = 16'b 0000_0000_0000_0000;
 377
 378                         1: assign RMASK_I = RADDR[   8] == 0 ? 16'b 1010_1010_1010_1010 :
 379                                             RADDR[   8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
 380
 381                         2: assign RMASK_I = RADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
 382                                             RADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
 383                                             RADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
 384                                             RADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
 385
 386                         3: assign RMASK_I = RADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
 387                                             RADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
 388                                             RADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
 389                                             RADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
 390                                             RADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
 391                                             RADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
 392                                             RADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
 393                                             RADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
 394                 endcase
 395
 396                 case (WRITE_MODE)
 397                         0: assign WDATA_I = WDATA;
 398
 399                         1: assign WDATA_I = {WDATA[14], WDATA[14], WDATA[12], WDATA[12],
 400                                              WDATA[10], WDATA[10], WDATA[ 8], WDATA[ 8],
 401                                              WDATA[ 6], WDATA[ 6], WDATA[ 4], WDATA[ 4],
 402                                              WDATA[ 2], WDATA[ 2], WDATA[ 0], WDATA[ 0]};
 403
 404                         2: assign WDATA_I = {WDATA[13], WDATA[13], WDATA[13], WDATA[13],
 405                                              WDATA[ 9], WDATA[ 9], WDATA[ 9], WDATA[ 9],
 406                                              WDATA[ 5], WDATA[ 5], WDATA[ 5], WDATA[ 5],
 407                                              WDATA[ 1], WDATA[ 1], WDATA[ 1], WDATA[ 1]};
 408
 409                         3: assign WDATA_I = {WDATA[11], WDATA[11], WDATA[11], WDATA[11],
 410                                              WDATA[11], WDATA[11], WDATA[11], WDATA[11],
 411                                              WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3],
 412                                              WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3]};
 413                 endcase
 414
 415                 case (READ_MODE)
 416                         0: assign RDATA = RDATA_I;
 417                         1: assign RDATA = {1'b0, |RDATA_I[15:14], 1'b0, |RDATA_I[13:12], 1'b0, |RDATA_I[11:10], 1'b0, |RDATA_I[ 9: 8],
 418                                            1'b0, |RDATA_I[ 7: 6], 1'b0, |RDATA_I[ 5: 4], 1'b0, |RDATA_I[ 3: 2], 1'b0, |RDATA_I[ 1: 0]};
 419                         2: assign RDATA = {2'b0, |RDATA_I[15:12], 3'b0, |RDATA_I[11: 8], 3'b0, |RDATA_I[ 7: 4], 3'b0, |RDATA_I[ 3: 0], 1'b0};
 420                         3: assign RDATA = {4'b0, |RDATA_I[15: 8], 7'b0, |RDATA_I[ 7: 0], 3'b0};
 421                 endcase
 422         endgenerate
 423
 424         integer i;
 425         reg [15:0] memory [0:255];
 426
 427         initial begin
 428                 if (INIT_FILE != "")
 429                         $readmemh(INIT_FILE, memory);
 430                 else
 431                         for (i=0; i<16; i=i+1) begin
 432                                 memory[ 0*16 + i] = INIT_0[16*i +: 16];
 433                                 memory[ 1*16 + i] = INIT_1[16*i +: 16];
 434                                 memory[ 2*16 + i] = INIT_2[16*i +: 16];
 435                                 memory[ 3*16 + i] = INIT_3[16*i +: 16];
 436                                 memory[ 4*16 + i] = INIT_4[16*i +: 16];
 437                                 memory[ 5*16 + i] = INIT_5[16*i +: 16];
 438                                 memory[ 6*16 + i] = INIT_6[16*i +: 16];
 439                                 memory[ 7*16 + i] = INIT_7[16*i +: 16];
 440                                 memory[ 8*16 + i] = INIT_8[16*i +: 16];
 441                                 memory[ 9*16 + i] = INIT_9[16*i +: 16];
 442                                 memory[10*16 + i] = INIT_A[16*i +: 16];
 443                                 memory[11*16 + i] = INIT_B[16*i +: 16];
 444                                 memory[12*16 + i] = INIT_C[16*i +: 16];
 445                                 memory[13*16 + i] = INIT_D[16*i +: 16];
 446                                 memory[14*16 + i] = INIT_E[16*i +: 16];
 447                                 memory[15*16 + i] = INIT_F[16*i +: 16];
 448                         end
 449         end
 450
 451         always @(posedge WCLK) begin
 452                 if (WE && WCLKE) begin
 453                         if (!WMASK_I[ 0]) memory[WADDR[7:0]][ 0] <= WDATA_I[ 0];
 454                         if (!WMASK_I[ 1]) memory[WADDR[7:0]][ 1] <= WDATA_I[ 1];
 455                         if (!WMASK_I[ 2]) memory[WADDR[7:0]][ 2] <= WDATA_I[ 2];
 456                         if (!WMASK_I[ 3]) memory[WADDR[7:0]][ 3] <= WDATA_I[ 3];
 457                         if (!WMASK_I[ 4]) memory[WADDR[7:0]][ 4] <= WDATA_I[ 4];
 458                         if (!WMASK_I[ 5]) memory[WADDR[7:0]][ 5] <= WDATA_I[ 5];
 459                         if (!WMASK_I[ 6]) memory[WADDR[7:0]][ 6] <= WDATA_I[ 6];
 460                         if (!WMASK_I[ 7]) memory[WADDR[7:0]][ 7] <= WDATA_I[ 7];
 461                         if (!WMASK_I[ 8]) memory[WADDR[7:0]][ 8] <= WDATA_I[ 8];
 462                         if (!WMASK_I[ 9]) memory[WADDR[7:0]][ 9] <= WDATA_I[ 9];
 463                         if (!WMASK_I[10]) memory[WADDR[7:0]][10] <= WDATA_I[10];
 464                         if (!WMASK_I[11]) memory[WADDR[7:0]][11] <= WDATA_I[11];
 465                         if (!WMASK_I[12]) memory[WADDR[7:0]][12] <= WDATA_I[12];
 466                         if (!WMASK_I[13]) memory[WADDR[7:0]][13] <= WDATA_I[13];
 467                         if (!WMASK_I[14]) memory[WADDR[7:0]][14] <= WDATA_I[14];
 468                         if (!WMASK_I[15]) memory[WADDR[7:0]][15] <= WDATA_I[15];
 469                 end
 470         end
 471
 472         always @(posedge RCLK) begin
 473                 if (RE && RCLKE) begin
 474                         RDATA_I <= memory[RADDR[7:0]] & ~RMASK_I;
 475                 end
 476         end
 477 `endif
 478 endmodule
 479
 480 module SB_RAM40_4KNR (
 481         (* abc_flop_q *) output [15:0] RDATA,
 482         input         RCLKN, RCLKE, RE,
 483         input  [10:0] RADDR,
 484         input         WCLK, WCLKE, WE,
 485         input  [10:0] WADDR,
 486         input  [15:0] MASK, WDATA
 487 );
 488         parameter WRITE_MODE = 0;
 489         parameter READ_MODE = 0;
 490
 491         parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 492         parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 493         parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 494         parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 495         parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 496         parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 497         parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 498         parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 499         parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 500         parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 501         parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 502         parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 503         parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 504         parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 505         parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 506         parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 507
 508         parameter INIT_FILE = "";
 509
 510         SB_RAM40_4K #(
 511                 .WRITE_MODE(WRITE_MODE),
 512                 .READ_MODE (READ_MODE ),
 513                 .INIT_0    (INIT_0    ),
 514                 .INIT_1    (INIT_1    ),
 515                 .INIT_2    (INIT_2    ),
 516                 .INIT_3    (INIT_3    ),
 517                 .INIT_4    (INIT_4    ),
 518                 .INIT_5    (INIT_5    ),
 519                 .INIT_6    (INIT_6    ),
 520                 .INIT_7    (INIT_7    ),
 521                 .INIT_8    (INIT_8    ),
 522                 .INIT_9    (INIT_9    ),
 523                 .INIT_A    (INIT_A    ),
 524                 .INIT_B    (INIT_B    ),
 525                 .INIT_C    (INIT_C    ),
 526                 .INIT_D    (INIT_D    ),
 527                 .INIT_E    (INIT_E    ),
 528                 .INIT_F    (INIT_F    ),
 529                 .INIT_FILE (INIT_FILE )
 530         ) RAM (
 531                 .RDATA(RDATA),
 532                 .RCLK (~RCLKN),
 533                 .RCLKE(RCLKE),
 534                 .RE   (RE   ),
 535                 .RADDR(RADDR),
 536                 .WCLK (WCLK ),
 537                 .WCLKE(WCLKE),
 538                 .WE   (WE   ),
 539                 .WADDR(WADDR),
 540                 .MASK (MASK ),
 541                 .WDATA(WDATA)
 542         );
 543 endmodule
 544
 545 module SB_RAM40_4KNW (
 546         (* abc_flop_q *) output [15:0] RDATA,
 547         input         RCLK, RCLKE, RE,
 548         input  [10:0] RADDR,
 549         input         WCLKN, WCLKE, WE,
 550         input  [10:0] WADDR,
 551         input  [15:0] MASK, WDATA
 552 );
 553         parameter WRITE_MODE = 0;
 554         parameter READ_MODE = 0;
 555
 556         parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 557         parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 558         parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 559         parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 560         parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 561         parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 562         parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 563         parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 564         parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 565         parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 566         parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 567         parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 568         parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 569         parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 570         parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 571         parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 572
 573         parameter INIT_FILE = "";
 574
 575         SB_RAM40_4K #(
 576                 .WRITE_MODE(WRITE_MODE),
 577                 .READ_MODE (READ_MODE ),
 578                 .INIT_0    (INIT_0    ),
 579                 .INIT_1    (INIT_1    ),
 580                 .INIT_2    (INIT_2    ),
 581                 .INIT_3    (INIT_3    ),
 582                 .INIT_4    (INIT_4    ),
 583                 .INIT_5    (INIT_5    ),
 584                 .INIT_6    (INIT_6    ),
 585                 .INIT_7    (INIT_7    ),
 586                 .INIT_8    (INIT_8    ),
 587                 .INIT_9    (INIT_9    ),
 588                 .INIT_A    (INIT_A    ),
 589                 .INIT_B    (INIT_B    ),
 590                 .INIT_C    (INIT_C    ),
 591                 .INIT_D    (INIT_D    ),
 592                 .INIT_E    (INIT_E    ),
 593                 .INIT_F    (INIT_F    ),
 594                 .INIT_FILE (INIT_FILE )
 595         ) RAM (
 596                 .RDATA(RDATA),
 597                 .RCLK (RCLK ),
 598                 .RCLKE(RCLKE),
 599                 .RE   (RE   ),
 600                 .RADDR(RADDR),
 601                 .WCLK (~WCLKN),
 602                 .WCLKE(WCLKE),
 603                 .WE   (WE   ),
 604                 .WADDR(WADDR),
 605                 .MASK (MASK ),
 606                 .WDATA(WDATA)
 607         );
 608 endmodule
 609
 610 module SB_RAM40_4KNRNW (
 611         (* abc_flop_q *) output [15:0] RDATA,
 612         input         RCLKN, RCLKE, RE,
 613         input  [10:0] RADDR,
 614         input         WCLKN, WCLKE, WE,
 615         input  [10:0] WADDR,
 616         input  [15:0] MASK, WDATA
 617 );
 618         parameter WRITE_MODE = 0;
 619         parameter READ_MODE = 0;
 620
 621         parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 622         parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 623         parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 624         parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 625         parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 626         parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 627         parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 628         parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 629         parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 630         parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 631         parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 632         parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 633         parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 634         parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 635         parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 636         parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 637
 638         parameter INIT_FILE = "";
 639
 640         SB_RAM40_4K #(
 641                 .WRITE_MODE(WRITE_MODE),
 642                 .READ_MODE (READ_MODE ),
 643                 .INIT_0    (INIT_0    ),
 644                 .INIT_1    (INIT_1    ),
 645                 .INIT_2    (INIT_2    ),
 646                 .INIT_3    (INIT_3    ),
 647                 .INIT_4    (INIT_4    ),
 648                 .INIT_5    (INIT_5    ),
 649                 .INIT_6    (INIT_6    ),
 650                 .INIT_7    (INIT_7    ),
 651                 .INIT_8    (INIT_8    ),
 652                 .INIT_9    (INIT_9    ),
 653                 .INIT_A    (INIT_A    ),
 654                 .INIT_B    (INIT_B    ),
 655                 .INIT_C    (INIT_C    ),
 656                 .INIT_D    (INIT_D    ),
 657                 .INIT_E    (INIT_E    ),
 658                 .INIT_F    (INIT_F    ),
 659                 .INIT_FILE (INIT_FILE )
 660         ) RAM (
 661                 .RDATA(RDATA),
 662                 .RCLK (~RCLKN),
 663                 .RCLKE(RCLKE),
 664                 .RE   (RE   ),
 665                 .RADDR(RADDR),
 666                 .WCLK (~WCLKN),
 667                 .WCLKE(WCLKE),
 668                 .WE   (WE   ),
 669                 .WADDR(WADDR),
 670                 .MASK (MASK ),
 671                 .WDATA(WDATA)
 672         );
 673 endmodule
 674
 675 // Packed IceStorm Logic Cells
 676
 677 module ICESTORM_LC (
 678         input I0, I1, I2, I3, CIN, CLK, CEN, SR,
 679         output LO, O, COUT
 680 );
 681         parameter [15:0] LUT_INIT = 0;
 682
 683         parameter [0:0] NEG_CLK      = 0;
 684         parameter [0:0] CARRY_ENABLE = 0;
 685         parameter [0:0] DFF_ENABLE   = 0;
 686         parameter [0:0] SET_NORESET  = 0;
 687         parameter [0:0] ASYNC_SR     = 0;
 688
 689         parameter [0:0] CIN_CONST    = 0;
 690         parameter [0:0] CIN_SET      = 0;
 691
 692         wire mux_cin = CIN_CONST ? CIN_SET : CIN;
 693
 694         assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && mux_cin) : 1'bx;
 695
 696         wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
 697         wire [3:0] lut_s2 = I2 ?   lut_s3[ 7:4] :   lut_s3[3:0];
 698         wire [1:0] lut_s1 = I1 ?   lut_s2[ 3:2] :   lut_s2[1:0];
 699         wire       lut_o  = I0 ?   lut_s1[   1] :   lut_s1[  0];
 700
 701         assign LO = lut_o;
 702
 703         wire polarized_clk;
 704         assign polarized_clk = CLK ^ NEG_CLK;
 705
 706         reg o_reg;
 707         always @(posedge polarized_clk)
 708                 if (CEN)
 709                         o_reg <= SR ? SET_NORESET : lut_o;
 710
 711         reg o_reg_async;
 712         always @(posedge polarized_clk, posedge SR)
 713                 if (SR)
 714                         o_reg <= SET_NORESET;
 715                 else if (CEN)
 716                         o_reg <= lut_o;
 717
 718         assign O = DFF_ENABLE ? ASYNC_SR ? o_reg_async : o_reg : lut_o;
 719 endmodule
 720
 721 // SiliconBlue PLL Cells
 722
 723 (* blackbox *)
 724 module SB_PLL40_CORE (
 725         input   REFERENCECLK,
 726         output  PLLOUTCORE,
 727         output  PLLOUTGLOBAL,
 728         input   EXTFEEDBACK,
 729         input   [7:0] DYNAMICDELAY,
 730         output  LOCK,
 731         input   BYPASS,
 732         input   RESETB,
 733         input   LATCHINPUTVALUE,
 734         output  SDO,
 735         input   SDI,
 736         input   SCLK
 737 );
 738         parameter FEEDBACK_PATH = "SIMPLE";
 739         parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
 740         parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
 741         parameter SHIFTREG_DIV_MODE = 1'b0;
 742         parameter FDA_FEEDBACK = 4'b0000;
 743         parameter FDA_RELATIVE = 4'b0000;
 744         parameter PLLOUT_SELECT = "GENCLK";
 745         parameter DIVR = 4'b0000;
 746         parameter DIVF = 7'b0000000;
 747         parameter DIVQ = 3'b000;
 748         parameter FILTER_RANGE = 3'b000;
 749         parameter ENABLE_ICEGATE = 1'b0;
 750         parameter TEST_MODE = 1'b0;
 751         parameter EXTERNAL_DIVIDE_FACTOR = 1;
 752 endmodule
 753
 754 (* blackbox *)
 755 module SB_PLL40_PAD (
 756         input   PACKAGEPIN,
 757         output  PLLOUTCORE,
 758         output  PLLOUTGLOBAL,
 759         input   EXTFEEDBACK,
 760         input   [7:0] DYNAMICDELAY,
 761         output  LOCK,
 762         input   BYPASS,
 763         input   RESETB,
 764         input   LATCHINPUTVALUE,
 765         output  SDO,
 766         input   SDI,
 767         input   SCLK
 768 );
 769         parameter FEEDBACK_PATH = "SIMPLE";
 770         parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
 771         parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
 772         parameter SHIFTREG_DIV_MODE = 1'b0;
 773         parameter FDA_FEEDBACK = 4'b0000;
 774         parameter FDA_RELATIVE = 4'b0000;
 775         parameter PLLOUT_SELECT = "GENCLK";
 776         parameter DIVR = 4'b0000;
 777         parameter DIVF = 7'b0000000;
 778         parameter DIVQ = 3'b000;
 779         parameter FILTER_RANGE = 3'b000;
 780         parameter ENABLE_ICEGATE = 1'b0;
 781         parameter TEST_MODE = 1'b0;
 782         parameter EXTERNAL_DIVIDE_FACTOR = 1;
 783 endmodule
 784
 785 (* blackbox *)
 786 module SB_PLL40_2_PAD (
 787         input   PACKAGEPIN,
 788         output  PLLOUTCOREA,
 789         output  PLLOUTGLOBALA,
 790         output  PLLOUTCOREB,
 791         output  PLLOUTGLOBALB,
 792         input   EXTFEEDBACK,
 793         input   [7:0] DYNAMICDELAY,
 794         output  LOCK,
 795         input   BYPASS,
 796         input   RESETB,
 797         input   LATCHINPUTVALUE,
 798         output  SDO,
 799         input   SDI,
 800         input   SCLK
 801 );
 802         parameter FEEDBACK_PATH = "SIMPLE";
 803         parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
 804         parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
 805         parameter SHIFTREG_DIV_MODE = 1'b0;
 806         parameter FDA_FEEDBACK = 4'b0000;
 807         parameter FDA_RELATIVE = 4'b0000;
 808         parameter PLLOUT_SELECT_PORTB = "GENCLK";
 809         parameter DIVR = 4'b0000;
 810         parameter DIVF = 7'b0000000;
 811         parameter DIVQ = 3'b000;
 812         parameter FILTER_RANGE = 3'b000;
 813         parameter ENABLE_ICEGATE_PORTA = 1'b0;
 814         parameter ENABLE_ICEGATE_PORTB = 1'b0;
 815         parameter TEST_MODE = 1'b0;
 816         parameter EXTERNAL_DIVIDE_FACTOR = 1;
 817 endmodule
 818
 819 (* blackbox *)
 820 module SB_PLL40_2F_CORE (
 821         input   REFERENCECLK,
 822         output  PLLOUTCOREA,
 823         output  PLLOUTGLOBALA,
 824         output  PLLOUTCOREB,
 825         output  PLLOUTGLOBALB,
 826         input   EXTFEEDBACK,
 827         input   [7:0] DYNAMICDELAY,
 828         output  LOCK,
 829         input   BYPASS,
 830         input   RESETB,
 831         input   LATCHINPUTVALUE,
 832         output  SDO,
 833         input   SDI,
 834         input   SCLK
 835 );
 836         parameter FEEDBACK_PATH = "SIMPLE";
 837         parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
 838         parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
 839         parameter SHIFTREG_DIV_MODE = 1'b0;
 840         parameter FDA_FEEDBACK = 4'b0000;
 841         parameter FDA_RELATIVE = 4'b0000;
 842         parameter PLLOUT_SELECT_PORTA = "GENCLK";
 843         parameter PLLOUT_SELECT_PORTB = "GENCLK";
 844         parameter DIVR = 4'b0000;
 845         parameter DIVF = 7'b0000000;
 846         parameter DIVQ = 3'b000;
 847         parameter FILTER_RANGE = 3'b000;
 848         parameter ENABLE_ICEGATE_PORTA = 1'b0;
 849         parameter ENABLE_ICEGATE_PORTB = 1'b0;
 850         parameter TEST_MODE = 1'b0;
 851         parameter EXTERNAL_DIVIDE_FACTOR = 1;
 852 endmodule
 853
 854 (* blackbox *)
 855 module SB_PLL40_2F_PAD (
 856         input   PACKAGEPIN,
 857         output  PLLOUTCOREA,
 858         output  PLLOUTGLOBALA,
 859         output  PLLOUTCOREB,
 860         output  PLLOUTGLOBALB,
 861         input   EXTFEEDBACK,
 862         input   [7:0] DYNAMICDELAY,
 863         output  LOCK,
 864         input   BYPASS,
 865         input   RESETB,
 866         input   LATCHINPUTVALUE,
 867         output  SDO,
 868         input   SDI,
 869         input   SCLK
 870 );
 871         parameter FEEDBACK_PATH = "SIMPLE";
 872         parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
 873         parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
 874         parameter SHIFTREG_DIV_MODE = 2'b00;
 875         parameter FDA_FEEDBACK = 4'b0000;
 876         parameter FDA_RELATIVE = 4'b0000;
 877         parameter PLLOUT_SELECT_PORTA = "GENCLK";
 878         parameter PLLOUT_SELECT_PORTB = "GENCLK";
 879         parameter DIVR = 4'b0000;
 880         parameter DIVF = 7'b0000000;
 881         parameter DIVQ = 3'b000;
 882         parameter FILTER_RANGE = 3'b000;
 883         parameter ENABLE_ICEGATE_PORTA = 1'b0;
 884         parameter ENABLE_ICEGATE_PORTB = 1'b0;
 885         parameter TEST_MODE = 1'b0;
 886         parameter EXTERNAL_DIVIDE_FACTOR = 1;
 887 endmodule
 888
 889 // SiliconBlue Device Configuration Cells
 890
 891 (* blackbox, keep *)
 892 module SB_WARMBOOT (
 893         input BOOT,
 894         input S1,
 895         input S0
 896 );
 897 endmodule
 898
 899 (* nomem2reg *)
 900 module SB_SPRAM256KA (
 901         input [13:0] ADDRESS,
 902         input [15:0] DATAIN,
 903         input [3:0] MASKWREN,
 904         input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
 905         (* abc_flop_q *) output reg [15:0] DATAOUT
 906 );
 907 `ifndef BLACKBOX
 908 `ifndef EQUIV
 909         reg [15:0] mem [0:16383];
 910         wire off = SLEEP || !POWEROFF;
 911         integer i;
 912
 913         always @(negedge POWEROFF) begin
 914                 for (i = 0; i <= 16383; i = i+1)
 915                         mem[i] = 'bx;
 916         end
 917
 918         always @(posedge CLOCK, posedge off) begin
 919                 if (off) begin
 920                         DATAOUT <= 0;
 921                 end else
 922                 if (CHIPSELECT && !STANDBY && !WREN) begin
 923                         DATAOUT <= mem[ADDRESS];
 924                 end else begin
 925                         if (CHIPSELECT && !STANDBY && WREN) begin
 926                                 if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0];
 927                                 if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4];
 928                                 if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8];
 929                                 if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12];
 930                         end
 931                         DATAOUT <= 'bx;
 932                 end
 933         end
 934 `endif
 935 `endif
 936 endmodule
 937
 938 (* blackbox *)
 939 module SB_HFOSC(
 940         input TRIM0,
 941         input TRIM1,
 942         input TRIM2,
 943         input TRIM3,
 944         input TRIM4,
 945         input TRIM5,
 946         input TRIM6,
 947         input TRIM7,
 948         input TRIM8,
 949         input TRIM9,
 950         input CLKHFPU,
 951         input CLKHFEN,
 952         output CLKHF
 953 );
 954 parameter TRIM_EN = "0b0";
 955 parameter CLKHF_DIV = "0b00";
 956 endmodule
 957
 958 (* blackbox *)
 959 module SB_LFOSC(
 960         input CLKLFPU,
 961         input CLKLFEN,
 962         output CLKLF
 963 );
 964 endmodule
 965
 966 (* blackbox *)
 967 module SB_RGBA_DRV(
 968         input CURREN,
 969         input RGBLEDEN,
 970         input RGB0PWM,
 971         input RGB1PWM,
 972         input RGB2PWM,
 973         output RGB0,
 974         output RGB1,
 975         output RGB2
 976 );
 977 parameter CURRENT_MODE = "0b0";
 978 parameter RGB0_CURRENT = "0b000000";
 979 parameter RGB1_CURRENT = "0b000000";
 980 parameter RGB2_CURRENT = "0b000000";
 981 endmodule
 982
 983 (* blackbox *)
 984 module SB_LED_DRV_CUR(
 985         input EN,
 986         output LEDPU
 987 );
 988 endmodule
 989
 990 (* blackbox *)
 991 module SB_RGB_DRV(
 992         input RGBLEDEN,
 993         input RGB0PWM,
 994         input RGB1PWM,
 995         input RGB2PWM,
 996         input RGBPU,
 997         output RGB0,
 998         output RGB1,
 999         output RGB2
1000 );
1001 parameter CURRENT_MODE = "0b0";
1002 parameter RGB0_CURRENT = "0b000000";
1003 parameter RGB1_CURRENT = "0b000000";
1004 parameter RGB2_CURRENT = "0b000000";
1005 endmodule
1006
1007 (* blackbox *)
1008 module SB_I2C(
1009         input  SBCLKI,
1010         input  SBRWI,
1011         input  SBSTBI,
1012         input  SBADRI7,
1013         input  SBADRI6,
1014         input  SBADRI5,
1015         input  SBADRI4,
1016         input  SBADRI3,
1017         input  SBADRI2,
1018         input  SBADRI1,
1019         input  SBADRI0,
1020         input  SBDATI7,
1021         input  SBDATI6,
1022         input  SBDATI5,
1023         input  SBDATI4,
1024         input  SBDATI3,
1025         input  SBDATI2,
1026         input  SBDATI1,
1027         input  SBDATI0,
1028         input  SCLI,
1029         input  SDAI,
1030         output SBDATO7,
1031         output SBDATO6,
1032         output SBDATO5,
1033         output SBDATO4,
1034         output SBDATO3,
1035         output SBDATO2,
1036         output SBDATO1,
1037         output SBDATO0,
1038         output SBACKO,
1039         output I2CIRQ,
1040         output I2CWKUP,
1041         output SCLO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
1042         output SCLOE,
1043         output SDAO,
1044         output SDAOE
1045 );
1046 parameter I2C_SLAVE_INIT_ADDR = "0b1111100001";
1047 parameter BUS_ADDR74 = "0b0001";
1048 endmodule
1049
1050 (* blackbox *)
1051 module SB_SPI (
1052         input  SBCLKI,
1053         input  SBRWI,
1054         input  SBSTBI,
1055         input  SBADRI7,
1056         input  SBADRI6,
1057         input  SBADRI5,
1058         input  SBADRI4,
1059         input  SBADRI3,
1060         input  SBADRI2,
1061         input  SBADRI1,
1062         input  SBADRI0,
1063         input  SBDATI7,
1064         input  SBDATI6,
1065         input  SBDATI5,
1066         input  SBDATI4,
1067         input  SBDATI3,
1068         input  SBDATI2,
1069         input  SBDATI1,
1070         input  SBDATI0,
1071         input  MI,
1072         input  SI,
1073         input  SCKI,
1074         input  SCSNI,
1075         output SBDATO7,
1076         output SBDATO6,
1077         output SBDATO5,
1078         output SBDATO4,
1079         output SBDATO3,
1080         output SBDATO2,
1081         output SBDATO1,
1082         output SBDATO0,
1083         output SBACKO,
1084         output SPIIRQ,
1085         output SPIWKUP,
1086         output SO,
1087         output SOE,
1088         output MO,
1089         output MOE,
1090         output SCKO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
1091         output SCKOE,
1092         output MCSNO3,
1093         output MCSNO2,
1094         output MCSNO1,
1095         output MCSNO0,
1096         output MCSNOE3,
1097         output MCSNOE2,
1098         output MCSNOE1,
1099         output MCSNOE0
1100 );
1101 parameter BUS_ADDR74 = "0b0000";
1102 endmodule
1103
1104 (* blackbox *)
1105 module SB_LEDDA_IP(
1106         input LEDDCS,
1107         input LEDDCLK,
1108         input LEDDDAT7,
1109         input LEDDDAT6,
1110         input LEDDDAT5,
1111         input LEDDDAT4,
1112         input LEDDDAT3,
1113         input LEDDDAT2,
1114         input LEDDDAT1,
1115         input LEDDDAT0,
1116         input LEDDADDR3,
1117         input LEDDADDR2,
1118         input LEDDADDR1,
1119         input LEDDADDR0,
1120         input LEDDDEN,
1121         input LEDDEXE,
1122         input LEDDRST,
1123         output PWMOUT0,
1124         output PWMOUT1,
1125         output PWMOUT2,
1126         output LEDDON
1127 );
1128 endmodule
1129
1130 (* blackbox *)
1131 module SB_FILTER_50NS(
1132         input FILTERIN,
1133         output FILTEROUT
1134 );
1135 endmodule
1136
1137 module SB_IO_I3C (
1138         inout  PACKAGE_PIN,
1139         input  LATCH_INPUT_VALUE,
1140         input  CLOCK_ENABLE,
1141         input  INPUT_CLK,
1142         input  OUTPUT_CLK,
1143         input  OUTPUT_ENABLE,
1144         input  D_OUT_0,
1145         input  D_OUT_1,
1146         output D_IN_0,
1147         output D_IN_1,
1148         input  PU_ENB,
1149         input  WEAK_PU_ENB
1150 );
1151         parameter [5:0] PIN_TYPE = 6'b000000;
1152         parameter [0:0] PULLUP = 1'b0;
1153         parameter [0:0] WEAK_PULLUP = 1'b0;
1154         parameter [0:0] NEG_TRIGGER = 1'b0;
1155         parameter IO_STANDARD = "SB_LVCMOS";
1156
1157 `ifndef BLACKBOX
1158         reg dout, din_0, din_1;
1159         reg din_q_0, din_q_1;
1160         reg dout_q_0, dout_q_1;
1161         reg outena_q;
1162
1163         generate if (!NEG_TRIGGER) begin
1164                 always @(posedge INPUT_CLK)  if (CLOCK_ENABLE) din_q_0  <= PACKAGE_PIN;
1165                 always @(negedge INPUT_CLK)  if (CLOCK_ENABLE) din_q_1  <= PACKAGE_PIN;
1166                 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
1167                 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
1168                 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
1169         end else begin
1170                 always @(negedge INPUT_CLK)  if (CLOCK_ENABLE) din_q_0  <= PACKAGE_PIN;
1171                 always @(posedge INPUT_CLK)  if (CLOCK_ENABLE) din_q_1  <= PACKAGE_PIN;
1172                 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
1173                 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
1174                 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
1175         end endgenerate
1176
1177         always @* begin
1178                 if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
1179                         din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
1180                 din_1 = din_q_1;
1181         end
1182
1183         // work around simulation glitches on dout in DDR mode
1184         reg outclk_delayed_1;
1185         reg outclk_delayed_2;
1186         always @* outclk_delayed_1 <= OUTPUT_CLK;
1187         always @* outclk_delayed_2 <= outclk_delayed_1;
1188
1189         always @* begin
1190                 if (PIN_TYPE[3])
1191                         dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
1192                 else
1193                         dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
1194         end
1195
1196         assign D_IN_0 = din_0, D_IN_1 = din_1;
1197
1198         generate
1199                 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
1200                 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
1201                 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
1202         endgenerate
1203 `endif
1204 endmodule
1205
1206 module SB_IO_OD (
1207         inout  PACKAGEPIN,
1208         input  LATCHINPUTVALUE,
1209         input  CLOCKENABLE,
1210         input  INPUTCLK,
1211         input  OUTPUTCLK,
1212         input  OUTPUTENABLE,
1213         input  DOUT1,
1214         input  DOUT0,
1215         output DIN1,
1216         output DIN0
1217 );
1218         parameter [5:0] PIN_TYPE = 6'b000000;
1219         parameter [0:0] NEG_TRIGGER = 1'b0;
1220
1221 `ifndef BLACKBOX
1222         reg dout, din_0, din_1;
1223         reg din_q_0, din_q_1;
1224         reg dout_q_0, dout_q_1;
1225         reg outena_q;
1226
1227         generate if (!NEG_TRIGGER) begin
1228                 always @(posedge INPUTCLK)  if (CLOCKENABLE) din_q_0  <= PACKAGEPIN;
1229                 always @(negedge INPUTCLK)  if (CLOCKENABLE) din_q_1  <= PACKAGEPIN;
1230                 always @(posedge OUTPUTCLK) if (CLOCKENABLE) dout_q_0 <= DOUT0;
1231                 always @(negedge OUTPUTCLK) if (CLOCKENABLE) dout_q_1 <= DOUT1;
1232                 always @(posedge OUTPUTCLK) if (CLOCKENABLE) outena_q <= OUTPUTENABLE;
1233         end else begin
1234                 always @(negedge INPUTCLK)  if (CLOCKENABLE) din_q_0  <= PACKAGEPIN;
1235                 always @(posedge INPUTCLK)  if (CLOCKENABLE) din_q_1  <= PACKAGEPIN;
1236                 always @(negedge OUTPUTCLK) if (CLOCKENABLE) dout_q_0 <= DOUT0;
1237                 always @(posedge OUTPUTCLK) if (CLOCKENABLE) dout_q_1 <= DOUT1;
1238                 always @(negedge OUTPUTCLK) if (CLOCKENABLE) outena_q <= OUTPUTENABLE;
1239         end endgenerate
1240
1241         always @* begin
1242                 if (!PIN_TYPE[1] || !LATCHINPUTVALUE)
1243                         din_0 = PIN_TYPE[0] ? PACKAGEPIN : din_q_0;
1244                 din_1 = din_q_1;
1245         end
1246
1247         // work around simulation glitches on dout in DDR mode
1248         reg outclk_delayed_1;
1249         reg outclk_delayed_2;
1250         always @* outclk_delayed_1 <= OUTPUTCLK;
1251         always @* outclk_delayed_2 <= outclk_delayed_1;
1252
1253         always @* begin
1254                 if (PIN_TYPE[3])
1255                         dout = PIN_TYPE[2] ? !dout_q_0 : DOUT0;
1256                 else
1257                         dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
1258         end
1259
1260         assign DIN0 = din_0, DIN1 = din_1;
1261
1262         generate
1263                 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGEPIN = dout ? 1'bz : 1'b0;
1264                 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGEPIN = OUTPUTENABLE ? (dout ? 1'bz : 1'b0) : 1'bz;
1265                 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGEPIN = outena_q ? (dout ? 1'bz : 1'b0) : 1'bz;
1266         endgenerate
1267 `endif
1268 endmodule
1269
1270 module SB_MAC16 (
1271         input CLK, CE,
1272         input [15:0] C, A, B, D,
1273         input AHOLD, BHOLD, CHOLD, DHOLD,
1274         input IRSTTOP, IRSTBOT,
1275         input ORSTTOP, ORSTBOT,
1276         input OLOADTOP, OLOADBOT,
1277         input ADDSUBTOP, ADDSUBBOT,
1278         input OHOLDTOP, OHOLDBOT,
1279         input CI, ACCUMCI, SIGNEXTIN,
1280         output [31:0] O,
1281         output CO, ACCUMCO, SIGNEXTOUT
1282 );
1283         parameter [0:0] NEG_TRIGGER = 0;
1284         parameter [0:0] C_REG = 0;
1285         parameter [0:0] A_REG = 0;
1286         parameter [0:0] B_REG = 0;
1287         parameter [0:0] D_REG = 0;
1288         parameter [0:0] TOP_8x8_MULT_REG = 0;
1289         parameter [0:0] BOT_8x8_MULT_REG = 0;
1290         parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
1291         parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
1292         parameter [1:0] TOPOUTPUT_SELECT = 0;
1293         parameter [1:0] TOPADDSUB_LOWERINPUT = 0;
1294         parameter [0:0] TOPADDSUB_UPPERINPUT = 0;
1295         parameter [1:0] TOPADDSUB_CARRYSELECT = 0;
1296         parameter [1:0] BOTOUTPUT_SELECT = 0;
1297         parameter [1:0] BOTADDSUB_LOWERINPUT = 0;
1298         parameter [0:0] BOTADDSUB_UPPERINPUT = 0;
1299         parameter [1:0] BOTADDSUB_CARRYSELECT = 0;
1300         parameter [0:0] MODE_8x8 = 0;
1301         parameter [0:0] A_SIGNED = 0;
1302         parameter [0:0] B_SIGNED = 0;
1303
1304         wire clock = CLK ^ NEG_TRIGGER;
1305
1306         // internal wires, compare Figure on page 133 of ICE Technology Library 3.0 and Fig 2 on page 2 of Lattice TN1295-DSP
1307         // http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201608.pdf
1308         // https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/AD/DSPFunctionUsageGuideforICE40Devices.ashx
1309         wire [15:0] iA, iB, iC, iD;
1310         wire [15:0] iF, iJ, iK, iG;
1311         wire [31:0] iL, iH;
1312         wire [15:0] iW, iX, iP, iQ;
1313         wire [15:0] iY, iZ, iR, iS;
1314         wire HCI, LCI, LCO;
1315
1316         // Regs C and A
1317         reg [15:0] rC, rA;
1318         always @(posedge clock, posedge IRSTTOP) begin
1319                 if (IRSTTOP) begin
1320                         rC <= 0;
1321                         rA <= 0;
1322                 end else if (CE) begin
1323                         if (!CHOLD) rC <= C;
1324                         if (!AHOLD) rA <= A;
1325                 end
1326         end
1327         assign iC = C_REG ? rC : C;
1328         assign iA = A_REG ? rA : A;
1329
1330         // Regs B and D
1331         reg [15:0] rB, rD;
1332         always @(posedge clock, posedge IRSTBOT) begin
1333                 if (IRSTBOT) begin
1334                         rB <= 0;
1335                         rD <= 0;
1336                 end else if (CE) begin
1337                         if (!BHOLD) rB <= B;
1338                         if (!DHOLD) rD <= D;
1339                 end
1340         end
1341         assign iB = B_REG ? rB : B;
1342         assign iD = D_REG ? rD : D;
1343
1344         // Multiplier Stage
1345         wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
1346         wire [15:0] Ah, Al, Bh, Bl;
1347         assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]};
1348         assign Al = {A_SIGNED ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
1349         assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]};
1350         assign Bl = {B_SIGNED ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
1351         assign p_Ah_Bh = Ah * Bh;
1352         assign p_Al_Bh = Al * Bh;
1353         assign p_Ah_Bl = Ah * Bl;
1354         assign p_Al_Bl = Al * Bl;
1355
1356         // Regs F and J
1357         reg [15:0] rF, rJ;
1358         always @(posedge clock, posedge IRSTTOP) begin
1359                 if (IRSTTOP) begin
1360                         rF <= 0;
1361                         rJ <= 0;
1362                 end else if (CE) begin
1363                         rF <= p_Ah_Bh;
1364                         if (!MODE_8x8) rJ <= p_Al_Bh;
1365                 end
1366         end
1367         assign iF = TOP_8x8_MULT_REG ? rF : p_Ah_Bh;
1368         assign iJ = PIPELINE_16x16_MULT_REG1 ? rJ : p_Al_Bh;
1369
1370         // Regs K and G
1371         reg [15:0] rK, rG;
1372         always @(posedge clock, posedge IRSTBOT) begin
1373                 if (IRSTBOT) begin
1374                         rK <= 0;
1375                         rG <= 0;
1376                 end else if (CE) begin
1377                         if (!MODE_8x8) rK <= p_Ah_Bl;
1378                         rG <= p_Al_Bl;
1379                 end
1380         end
1381         assign iK = PIPELINE_16x16_MULT_REG1 ? rK : p_Ah_Bl;
1382         assign iG = BOT_8x8_MULT_REG ? rG : p_Al_Bl;
1383
1384         // Adder Stage
1385         assign iL = iG + (iK << 8) + (iJ << 8) + (iF << 16);
1386
1387         // Reg H
1388         reg [31:0] rH;
1389         always @(posedge clock, posedge IRSTBOT) begin
1390                 if (IRSTBOT) begin
1391                         rH <= 0;
1392                 end else if (CE) begin
1393                         if (!MODE_8x8) rH <= iL;
1394                 end
1395         end
1396         assign iH = PIPELINE_16x16_MULT_REG2 ? rH : iL;
1397
1398         // Hi Output Stage
1399         wire [15:0] XW, Oh;
1400         reg [15:0] rQ;
1401         assign iW = TOPADDSUB_UPPERINPUT ? iC : iQ;
1402         assign iX = (TOPADDSUB_LOWERINPUT == 0) ? iA : (TOPADDSUB_LOWERINPUT == 1) ? iF : (TOPADDSUB_LOWERINPUT == 2) ? iH[31:16] : {16{iZ[15]}};
1403         assign {ACCUMCO, XW} = iX + (iW ^ {16{ADDSUBTOP}}) + HCI;
1404         assign CO = ACCUMCO ^ ADDSUBTOP;
1405         assign iP = OLOADTOP ? iC : XW ^ {16{ADDSUBTOP}};
1406         always @(posedge clock, posedge ORSTTOP) begin
1407                 if (ORSTTOP) begin
1408                         rQ <= 0;
1409                 end else if (CE) begin
1410                         if (!OHOLDTOP) rQ <= iP;
1411                 end
1412         end
1413         assign iQ = rQ;
1414         assign Oh = (TOPOUTPUT_SELECT == 0) ? iP : (TOPOUTPUT_SELECT == 1) ? iQ : (TOPOUTPUT_SELECT == 2) ? iF : iH[31:16];
1415         assign HCI = (TOPADDSUB_CARRYSELECT == 0) ? 1'b0 : (TOPADDSUB_CARRYSELECT == 1) ? 1'b1 : (TOPADDSUB_CARRYSELECT == 2) ? LCO : LCO ^ ADDSUBBOT;
1416         assign SIGNEXTOUT = iX[15];
1417
1418         // Lo Output Stage
1419         wire [15:0] YZ, Ol;
1420         reg [15:0] rS;
1421         assign iY = BOTADDSUB_UPPERINPUT ? iD : iS;
1422         assign iZ = (BOTADDSUB_LOWERINPUT == 0) ? iB : (BOTADDSUB_LOWERINPUT == 1) ? iG : (BOTADDSUB_LOWERINPUT == 2) ? iH[15:0] : {16{SIGNEXTIN}};
1423         assign {LCO, YZ} = iZ + (iY ^ {16{ADDSUBBOT}}) + LCI;
1424         assign iR = OLOADBOT ? iD : YZ ^ {16{ADDSUBBOT}};
1425         always @(posedge clock, posedge ORSTBOT) begin
1426                 if (ORSTBOT) begin
1427                         rS <= 0;
1428                 end else if (CE) begin
1429                         if (!OHOLDBOT) rS <= iR;
1430                 end
1431         end
1432         assign iS = rS;
1433         assign Ol = (BOTOUTPUT_SELECT == 0) ? iR : (BOTOUTPUT_SELECT == 1) ? iS : (BOTOUTPUT_SELECT == 2) ? iG : iH[15:0];
1434         assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI;
1435         assign O = {Oh, Ol};
1436 endmodule