2 `define SB_DFF_REG reg Q = 0
3 // `define SB_DFF_REG reg Q
5 // SiliconBlue IO Cells
9 input LATCH_INPUT_VALUE,
19 parameter [5:0] PIN_TYPE = 6'b000000;
20 parameter [0:0] PULLUP = 1'b0;
21 parameter [0:0] NEG_TRIGGER = 1'b0;
22 parameter IO_STANDARD = "SB_LVCMOS";
25 reg dout, din_0, din_1;
27 reg dout_q_0, dout_q_1;
30 // IO tile generates a constant 1'b1 internally if global_cen is not connected
31 wire clken_pulled = CLOCK_ENABLE || CLOCK_ENABLE === 1'bz;
35 generate if (!NEG_TRIGGER) begin
36 always @(posedge INPUT_CLK) clken_pulled_ri <= clken_pulled;
37 always @(posedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN;
38 always @(negedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN;
39 always @(posedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled;
40 always @(posedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0;
41 always @(negedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1;
42 always @(posedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE;
44 always @(negedge INPUT_CLK) clken_pulled_ri <= clken_pulled;
45 always @(negedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN;
46 always @(posedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN;
47 always @(negedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled;
48 always @(negedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0;
49 always @(posedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1;
50 always @(negedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE;
54 if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
55 din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
59 // work around simulation glitches on dout in DDR mode
62 always @* outclk_delayed_1 <= OUTPUT_CLK;
63 always @* outclk_delayed_2 <= outclk_delayed_1;
67 dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
69 dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
72 assign D_IN_0 = din_0, D_IN_1 = din_1;
75 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
76 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
77 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
84 output GLOBAL_BUFFER_OUTPUT,
85 input LATCH_INPUT_VALUE,
95 parameter [5:0] PIN_TYPE = 6'b000000;
96 parameter [0:0] PULLUP = 1'b0;
97 parameter [0:0] NEG_TRIGGER = 1'b0;
98 parameter IO_STANDARD = "SB_LVCMOS";
100 assign GLOBAL_BUFFER_OUTPUT = PACKAGE_PIN;
105 .NEG_TRIGGER(NEG_TRIGGER),
106 .IO_STANDARD(IO_STANDARD)
108 .PACKAGE_PIN(PACKAGE_PIN),
109 .LATCH_INPUT_VALUE(LATCH_INPUT_VALUE),
110 .CLOCK_ENABLE(CLOCK_ENABLE),
111 .INPUT_CLK(INPUT_CLK),
112 .OUTPUT_CLK(OUTPUT_CLK),
113 .OUTPUT_ENABLE(OUTPUT_ENABLE),
122 input USER_SIGNAL_TO_GLOBAL_BUFFER,
123 output GLOBAL_BUFFER_OUTPUT
125 assign GLOBAL_BUFFER_OUTPUT = USER_SIGNAL_TO_GLOBAL_BUFFER;
128 // SiliconBlue Logic Cells
130 (* abc_box_id = 2, lib_whitebox *)
131 module SB_LUT4 (output O, input I0, I1, I2, I3);
132 parameter [15:0] LUT_INIT = 0;
133 wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
134 wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
135 wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];
136 assign O = I0 ? s1[1] : s1[0];
139 (* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
140 module SB_CARRY (output CO, input I0, I1, CI);
141 assign CO = (I0 && I1) || ((I0 || I1) && CI);
144 // Positive Edge SiliconBlue FF Cells
146 module SB_DFF (output `SB_DFF_REG, input C, D);
151 module SB_DFFE (output `SB_DFF_REG, input C, E, D);
157 module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
165 module SB_DFFR (output `SB_DFF_REG, input C, R, D);
166 always @(posedge C, posedge R)
173 module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
181 module SB_DFFS (output `SB_DFF_REG, input C, S, D);
182 always @(posedge C, posedge S)
189 module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
199 module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
200 always @(posedge C, posedge R)
207 module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
217 module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
218 always @(posedge C, posedge S)
225 // Negative Edge SiliconBlue FF Cells
227 module SB_DFFN (output `SB_DFF_REG, input C, D);
232 module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
238 module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
246 module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
247 always @(negedge C, posedge R)
254 module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
262 module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
263 always @(negedge C, posedge S)
270 module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
280 module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
281 always @(negedge C, posedge R)
288 module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
298 module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
299 always @(negedge C, posedge S)
306 // SiliconBlue RAM Cells
310 input RCLK, RCLKE, RE,
312 input WCLK, WCLKE, WE,
314 input [15:0] MASK, WDATA
320 parameter WRITE_MODE = 0;
321 parameter READ_MODE = 0;
323 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
324 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
325 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
326 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
327 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
328 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
329 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
330 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
331 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
332 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
333 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
334 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
335 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
336 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
337 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
338 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
340 parameter INIT_FILE = "";
351 0: assign WMASK_I = MASK;
353 1: assign WMASK_I = WADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
354 WADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
356 2: assign WMASK_I = WADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
357 WADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
358 WADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
359 WADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
361 3: assign WMASK_I = WADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
362 WADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
363 WADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
364 WADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
365 WADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
366 WADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
367 WADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
368 WADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
372 0: assign RMASK_I = 16'b 0000_0000_0000_0000;
374 1: assign RMASK_I = RADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
375 RADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
377 2: assign RMASK_I = RADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
378 RADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
379 RADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
380 RADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
382 3: assign RMASK_I = RADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
383 RADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
384 RADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
385 RADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
386 RADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
387 RADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
388 RADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
389 RADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
393 0: assign WDATA_I = WDATA;
395 1: assign WDATA_I = {WDATA[14], WDATA[14], WDATA[12], WDATA[12],
396 WDATA[10], WDATA[10], WDATA[ 8], WDATA[ 8],
397 WDATA[ 6], WDATA[ 6], WDATA[ 4], WDATA[ 4],
398 WDATA[ 2], WDATA[ 2], WDATA[ 0], WDATA[ 0]};
400 2: assign WDATA_I = {WDATA[13], WDATA[13], WDATA[13], WDATA[13],
401 WDATA[ 9], WDATA[ 9], WDATA[ 9], WDATA[ 9],
402 WDATA[ 5], WDATA[ 5], WDATA[ 5], WDATA[ 5],
403 WDATA[ 1], WDATA[ 1], WDATA[ 1], WDATA[ 1]};
405 3: assign WDATA_I = {WDATA[11], WDATA[11], WDATA[11], WDATA[11],
406 WDATA[11], WDATA[11], WDATA[11], WDATA[11],
407 WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3],
408 WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3]};
412 0: assign RDATA = RDATA_I;
413 1: assign RDATA = {1'b0, |RDATA_I[15:14], 1'b0, |RDATA_I[13:12], 1'b0, |RDATA_I[11:10], 1'b0, |RDATA_I[ 9: 8],
414 1'b0, |RDATA_I[ 7: 6], 1'b0, |RDATA_I[ 5: 4], 1'b0, |RDATA_I[ 3: 2], 1'b0, |RDATA_I[ 1: 0]};
415 2: assign RDATA = {2'b0, |RDATA_I[15:12], 3'b0, |RDATA_I[11: 8], 3'b0, |RDATA_I[ 7: 4], 3'b0, |RDATA_I[ 3: 0], 1'b0};
416 3: assign RDATA = {4'b0, |RDATA_I[15: 8], 7'b0, |RDATA_I[ 7: 0], 3'b0};
421 reg [15:0] memory [0:255];
425 $readmemh(INIT_FILE, memory);
427 for (i=0; i<16; i=i+1) begin
428 memory[ 0*16 + i] = INIT_0[16*i +: 16];
429 memory[ 1*16 + i] = INIT_1[16*i +: 16];
430 memory[ 2*16 + i] = INIT_2[16*i +: 16];
431 memory[ 3*16 + i] = INIT_3[16*i +: 16];
432 memory[ 4*16 + i] = INIT_4[16*i +: 16];
433 memory[ 5*16 + i] = INIT_5[16*i +: 16];
434 memory[ 6*16 + i] = INIT_6[16*i +: 16];
435 memory[ 7*16 + i] = INIT_7[16*i +: 16];
436 memory[ 8*16 + i] = INIT_8[16*i +: 16];
437 memory[ 9*16 + i] = INIT_9[16*i +: 16];
438 memory[10*16 + i] = INIT_A[16*i +: 16];
439 memory[11*16 + i] = INIT_B[16*i +: 16];
440 memory[12*16 + i] = INIT_C[16*i +: 16];
441 memory[13*16 + i] = INIT_D[16*i +: 16];
442 memory[14*16 + i] = INIT_E[16*i +: 16];
443 memory[15*16 + i] = INIT_F[16*i +: 16];
447 always @(posedge WCLK) begin
448 if (WE && WCLKE) begin
449 if (!WMASK_I[ 0]) memory[WADDR[7:0]][ 0] <= WDATA_I[ 0];
450 if (!WMASK_I[ 1]) memory[WADDR[7:0]][ 1] <= WDATA_I[ 1];
451 if (!WMASK_I[ 2]) memory[WADDR[7:0]][ 2] <= WDATA_I[ 2];
452 if (!WMASK_I[ 3]) memory[WADDR[7:0]][ 3] <= WDATA_I[ 3];
453 if (!WMASK_I[ 4]) memory[WADDR[7:0]][ 4] <= WDATA_I[ 4];
454 if (!WMASK_I[ 5]) memory[WADDR[7:0]][ 5] <= WDATA_I[ 5];
455 if (!WMASK_I[ 6]) memory[WADDR[7:0]][ 6] <= WDATA_I[ 6];
456 if (!WMASK_I[ 7]) memory[WADDR[7:0]][ 7] <= WDATA_I[ 7];
457 if (!WMASK_I[ 8]) memory[WADDR[7:0]][ 8] <= WDATA_I[ 8];
458 if (!WMASK_I[ 9]) memory[WADDR[7:0]][ 9] <= WDATA_I[ 9];
459 if (!WMASK_I[10]) memory[WADDR[7:0]][10] <= WDATA_I[10];
460 if (!WMASK_I[11]) memory[WADDR[7:0]][11] <= WDATA_I[11];
461 if (!WMASK_I[12]) memory[WADDR[7:0]][12] <= WDATA_I[12];
462 if (!WMASK_I[13]) memory[WADDR[7:0]][13] <= WDATA_I[13];
463 if (!WMASK_I[14]) memory[WADDR[7:0]][14] <= WDATA_I[14];
464 if (!WMASK_I[15]) memory[WADDR[7:0]][15] <= WDATA_I[15];
468 always @(posedge RCLK) begin
469 if (RE && RCLKE) begin
470 RDATA_I <= memory[RADDR[7:0]] & ~RMASK_I;
476 module SB_RAM40_4KNR (
478 input RCLKN, RCLKE, RE,
480 input WCLK, WCLKE, WE,
482 input [15:0] MASK, WDATA
484 parameter WRITE_MODE = 0;
485 parameter READ_MODE = 0;
487 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
488 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
489 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
490 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
491 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
492 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
493 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
494 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
495 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
496 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
497 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
498 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
499 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
500 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
501 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
502 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
504 parameter INIT_FILE = "";
507 .WRITE_MODE(WRITE_MODE),
508 .READ_MODE (READ_MODE ),
525 .INIT_FILE (INIT_FILE )
541 module SB_RAM40_4KNW (
543 input RCLK, RCLKE, RE,
545 input WCLKN, WCLKE, WE,
547 input [15:0] MASK, WDATA
549 parameter WRITE_MODE = 0;
550 parameter READ_MODE = 0;
552 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
553 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
554 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
555 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
556 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
557 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
558 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
559 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
560 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
561 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
562 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
563 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
564 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
565 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
566 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
567 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
569 parameter INIT_FILE = "";
572 .WRITE_MODE(WRITE_MODE),
573 .READ_MODE (READ_MODE ),
590 .INIT_FILE (INIT_FILE )
606 module SB_RAM40_4KNRNW (
608 input RCLKN, RCLKE, RE,
610 input WCLKN, WCLKE, WE,
612 input [15:0] MASK, WDATA
614 parameter WRITE_MODE = 0;
615 parameter READ_MODE = 0;
617 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
618 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
619 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
620 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
621 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
622 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
623 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
624 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
625 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
626 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
627 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
628 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
629 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
630 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
631 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
632 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
634 parameter INIT_FILE = "";
637 .WRITE_MODE(WRITE_MODE),
638 .READ_MODE (READ_MODE ),
655 .INIT_FILE (INIT_FILE )
671 // Packed IceStorm Logic Cells
674 input I0, I1, I2, I3, CIN, CLK, CEN, SR,
677 parameter [15:0] LUT_INIT = 0;
679 parameter [0:0] NEG_CLK = 0;
680 parameter [0:0] CARRY_ENABLE = 0;
681 parameter [0:0] DFF_ENABLE = 0;
682 parameter [0:0] SET_NORESET = 0;
683 parameter [0:0] ASYNC_SR = 0;
685 parameter [0:0] CIN_CONST = 0;
686 parameter [0:0] CIN_SET = 0;
688 wire mux_cin = CIN_CONST ? CIN_SET : CIN;
690 assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && mux_cin) : 1'bx;
692 wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
693 wire [3:0] lut_s2 = I2 ? lut_s3[ 7:4] : lut_s3[3:0];
694 wire [1:0] lut_s1 = I1 ? lut_s2[ 3:2] : lut_s2[1:0];
695 wire lut_o = I0 ? lut_s1[ 1] : lut_s1[ 0];
700 assign polarized_clk = CLK ^ NEG_CLK;
703 always @(posedge polarized_clk)
705 o_reg <= SR ? SET_NORESET : lut_o;
708 always @(posedge polarized_clk, posedge SR)
710 o_reg <= SET_NORESET;
714 assign O = DFF_ENABLE ? ASYNC_SR ? o_reg_async : o_reg : lut_o;
717 // SiliconBlue PLL Cells
720 module SB_PLL40_CORE (
725 input [7:0] DYNAMICDELAY,
729 input LATCHINPUTVALUE,
734 parameter FEEDBACK_PATH = "SIMPLE";
735 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
736 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
737 parameter SHIFTREG_DIV_MODE = 1'b0;
738 parameter FDA_FEEDBACK = 4'b0000;
739 parameter FDA_RELATIVE = 4'b0000;
740 parameter PLLOUT_SELECT = "GENCLK";
741 parameter DIVR = 4'b0000;
742 parameter DIVF = 7'b0000000;
743 parameter DIVQ = 3'b000;
744 parameter FILTER_RANGE = 3'b000;
745 parameter ENABLE_ICEGATE = 1'b0;
746 parameter TEST_MODE = 1'b0;
747 parameter EXTERNAL_DIVIDE_FACTOR = 1;
751 module SB_PLL40_PAD (
756 input [7:0] DYNAMICDELAY,
760 input LATCHINPUTVALUE,
765 parameter FEEDBACK_PATH = "SIMPLE";
766 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
767 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
768 parameter SHIFTREG_DIV_MODE = 1'b0;
769 parameter FDA_FEEDBACK = 4'b0000;
770 parameter FDA_RELATIVE = 4'b0000;
771 parameter PLLOUT_SELECT = "GENCLK";
772 parameter DIVR = 4'b0000;
773 parameter DIVF = 7'b0000000;
774 parameter DIVQ = 3'b000;
775 parameter FILTER_RANGE = 3'b000;
776 parameter ENABLE_ICEGATE = 1'b0;
777 parameter TEST_MODE = 1'b0;
778 parameter EXTERNAL_DIVIDE_FACTOR = 1;
782 module SB_PLL40_2_PAD (
785 output PLLOUTGLOBALA,
787 output PLLOUTGLOBALB,
789 input [7:0] DYNAMICDELAY,
793 input LATCHINPUTVALUE,
798 parameter FEEDBACK_PATH = "SIMPLE";
799 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
800 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
801 parameter SHIFTREG_DIV_MODE = 1'b0;
802 parameter FDA_FEEDBACK = 4'b0000;
803 parameter FDA_RELATIVE = 4'b0000;
804 parameter PLLOUT_SELECT_PORTB = "GENCLK";
805 parameter DIVR = 4'b0000;
806 parameter DIVF = 7'b0000000;
807 parameter DIVQ = 3'b000;
808 parameter FILTER_RANGE = 3'b000;
809 parameter ENABLE_ICEGATE_PORTA = 1'b0;
810 parameter ENABLE_ICEGATE_PORTB = 1'b0;
811 parameter TEST_MODE = 1'b0;
812 parameter EXTERNAL_DIVIDE_FACTOR = 1;
816 module SB_PLL40_2F_CORE (
819 output PLLOUTGLOBALA,
821 output PLLOUTGLOBALB,
823 input [7:0] DYNAMICDELAY,
827 input LATCHINPUTVALUE,
832 parameter FEEDBACK_PATH = "SIMPLE";
833 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
834 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
835 parameter SHIFTREG_DIV_MODE = 1'b0;
836 parameter FDA_FEEDBACK = 4'b0000;
837 parameter FDA_RELATIVE = 4'b0000;
838 parameter PLLOUT_SELECT_PORTA = "GENCLK";
839 parameter PLLOUT_SELECT_PORTB = "GENCLK";
840 parameter DIVR = 4'b0000;
841 parameter DIVF = 7'b0000000;
842 parameter DIVQ = 3'b000;
843 parameter FILTER_RANGE = 3'b000;
844 parameter ENABLE_ICEGATE_PORTA = 1'b0;
845 parameter ENABLE_ICEGATE_PORTB = 1'b0;
846 parameter TEST_MODE = 1'b0;
847 parameter EXTERNAL_DIVIDE_FACTOR = 1;
851 module SB_PLL40_2F_PAD (
854 output PLLOUTGLOBALA,
856 output PLLOUTGLOBALB,
858 input [7:0] DYNAMICDELAY,
862 input LATCHINPUTVALUE,
867 parameter FEEDBACK_PATH = "SIMPLE";
868 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
869 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
870 parameter SHIFTREG_DIV_MODE = 2'b00;
871 parameter FDA_FEEDBACK = 4'b0000;
872 parameter FDA_RELATIVE = 4'b0000;
873 parameter PLLOUT_SELECT_PORTA = "GENCLK";
874 parameter PLLOUT_SELECT_PORTB = "GENCLK";
875 parameter DIVR = 4'b0000;
876 parameter DIVF = 7'b0000000;
877 parameter DIVQ = 3'b000;
878 parameter FILTER_RANGE = 3'b000;
879 parameter ENABLE_ICEGATE_PORTA = 1'b0;
880 parameter ENABLE_ICEGATE_PORTB = 1'b0;
881 parameter TEST_MODE = 1'b0;
882 parameter EXTERNAL_DIVIDE_FACTOR = 1;
885 // SiliconBlue Device Configuration Cells
895 module SB_SPRAM256KA (
896 input [13:0] ADDRESS,
898 input [3:0] MASKWREN,
899 input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
900 output reg [15:0] DATAOUT
904 reg [15:0] mem [0:16383];
905 wire off = SLEEP || !POWEROFF;
908 always @(negedge POWEROFF) begin
909 for (i = 0; i <= 16383; i = i+1)
913 always @(posedge CLOCK, posedge off) begin
917 if (CHIPSELECT && !STANDBY && !WREN) begin
918 DATAOUT <= mem[ADDRESS];
920 if (CHIPSELECT && !STANDBY && WREN) begin
921 if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0];
922 if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4];
923 if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8];
924 if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12];
949 parameter TRIM_EN = "0b0";
950 parameter CLKHF_DIV = "0b00";
972 parameter CURRENT_MODE = "0b0";
973 parameter RGB0_CURRENT = "0b000000";
974 parameter RGB1_CURRENT = "0b000000";
975 parameter RGB2_CURRENT = "0b000000";
979 module SB_LED_DRV_CUR(
996 parameter CURRENT_MODE = "0b0";
997 parameter RGB0_CURRENT = "0b000000";
998 parameter RGB1_CURRENT = "0b000000";
999 parameter RGB2_CURRENT = "0b000000";
1036 output SCLO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
1041 parameter I2C_SLAVE_INIT_ADDR = "0b1111100001";
1042 parameter BUS_ADDR74 = "0b0001";
1085 output SCKO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
1096 parameter BUS_ADDR74 = "0b0000";
1126 module SB_FILTER_50NS(
1134 input LATCH_INPUT_VALUE,
1138 input OUTPUT_ENABLE,
1146 parameter [5:0] PIN_TYPE = 6'b000000;
1147 parameter [0:0] PULLUP = 1'b0;
1148 parameter [0:0] WEAK_PULLUP = 1'b0;
1149 parameter [0:0] NEG_TRIGGER = 1'b0;
1150 parameter IO_STANDARD = "SB_LVCMOS";
1153 reg dout, din_0, din_1;
1154 reg din_q_0, din_q_1;
1155 reg dout_q_0, dout_q_1;
1158 generate if (!NEG_TRIGGER) begin
1159 always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
1160 always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
1161 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
1162 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
1163 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
1165 always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
1166 always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
1167 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
1168 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
1169 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
1173 if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
1174 din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
1178 // work around simulation glitches on dout in DDR mode
1179 reg outclk_delayed_1;
1180 reg outclk_delayed_2;
1181 always @* outclk_delayed_1 <= OUTPUT_CLK;
1182 always @* outclk_delayed_2 <= outclk_delayed_1;
1186 dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
1188 dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
1191 assign D_IN_0 = din_0, D_IN_1 = din_1;
1194 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
1195 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
1196 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
1203 input LATCHINPUTVALUE,
1213 parameter [5:0] PIN_TYPE = 6'b000000;
1214 parameter [0:0] NEG_TRIGGER = 1'b0;
1217 reg dout, din_0, din_1;
1218 reg din_q_0, din_q_1;
1219 reg dout_q_0, dout_q_1;
1222 generate if (!NEG_TRIGGER) begin
1223 always @(posedge INPUTCLK) if (CLOCKENABLE) din_q_0 <= PACKAGEPIN;
1224 always @(negedge INPUTCLK) if (CLOCKENABLE) din_q_1 <= PACKAGEPIN;
1225 always @(posedge OUTPUTCLK) if (CLOCKENABLE) dout_q_0 <= DOUT0;
1226 always @(negedge OUTPUTCLK) if (CLOCKENABLE) dout_q_1 <= DOUT1;
1227 always @(posedge OUTPUTCLK) if (CLOCKENABLE) outena_q <= OUTPUTENABLE;
1229 always @(negedge INPUTCLK) if (CLOCKENABLE) din_q_0 <= PACKAGEPIN;
1230 always @(posedge INPUTCLK) if (CLOCKENABLE) din_q_1 <= PACKAGEPIN;
1231 always @(negedge OUTPUTCLK) if (CLOCKENABLE) dout_q_0 <= DOUT0;
1232 always @(posedge OUTPUTCLK) if (CLOCKENABLE) dout_q_1 <= DOUT1;
1233 always @(negedge OUTPUTCLK) if (CLOCKENABLE) outena_q <= OUTPUTENABLE;
1237 if (!PIN_TYPE[1] || !LATCHINPUTVALUE)
1238 din_0 = PIN_TYPE[0] ? PACKAGEPIN : din_q_0;
1242 // work around simulation glitches on dout in DDR mode
1243 reg outclk_delayed_1;
1244 reg outclk_delayed_2;
1245 always @* outclk_delayed_1 <= OUTPUTCLK;
1246 always @* outclk_delayed_2 <= outclk_delayed_1;
1250 dout = PIN_TYPE[2] ? !dout_q_0 : DOUT0;
1252 dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
1255 assign DIN0 = din_0, DIN1 = din_1;
1258 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGEPIN = dout ? 1'bz : 1'b0;
1259 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGEPIN = OUTPUTENABLE ? (dout ? 1'bz : 1'b0) : 1'bz;
1260 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGEPIN = outena_q ? (dout ? 1'bz : 1'b0) : 1'bz;
1267 input [15:0] C, A, B, D,
1268 input AHOLD, BHOLD, CHOLD, DHOLD,
1269 input IRSTTOP, IRSTBOT,
1270 input ORSTTOP, ORSTBOT,
1271 input OLOADTOP, OLOADBOT,
1272 input ADDSUBTOP, ADDSUBBOT,
1273 input OHOLDTOP, OHOLDBOT,
1274 input CI, ACCUMCI, SIGNEXTIN,
1276 output CO, ACCUMCO, SIGNEXTOUT
1278 parameter [0:0] NEG_TRIGGER = 0;
1279 parameter [0:0] C_REG = 0;
1280 parameter [0:0] A_REG = 0;
1281 parameter [0:0] B_REG = 0;
1282 parameter [0:0] D_REG = 0;
1283 parameter [0:0] TOP_8x8_MULT_REG = 0;
1284 parameter [0:0] BOT_8x8_MULT_REG = 0;
1285 parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
1286 parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
1287 parameter [1:0] TOPOUTPUT_SELECT = 0;
1288 parameter [1:0] TOPADDSUB_LOWERINPUT = 0;
1289 parameter [0:0] TOPADDSUB_UPPERINPUT = 0;
1290 parameter [1:0] TOPADDSUB_CARRYSELECT = 0;
1291 parameter [1:0] BOTOUTPUT_SELECT = 0;
1292 parameter [1:0] BOTADDSUB_LOWERINPUT = 0;
1293 parameter [0:0] BOTADDSUB_UPPERINPUT = 0;
1294 parameter [1:0] BOTADDSUB_CARRYSELECT = 0;
1295 parameter [0:0] MODE_8x8 = 0;
1296 parameter [0:0] A_SIGNED = 0;
1297 parameter [0:0] B_SIGNED = 0;
1299 wire clock = CLK ^ NEG_TRIGGER;
1301 // internal wires, compare Figure on page 133 of ICE Technology Library 3.0 and Fig 2 on page 2 of Lattice TN1295-DSP
1302 // http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201608.pdf
1303 // https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/AD/DSPFunctionUsageGuideforICE40Devices.ashx
1304 wire [15:0] iA, iB, iC, iD;
1305 wire [15:0] iF, iJ, iK, iG;
1307 wire [15:0] iW, iX, iP, iQ;
1308 wire [15:0] iY, iZ, iR, iS;
1313 always @(posedge clock, posedge IRSTTOP) begin
1317 end else if (CE) begin
1318 if (!CHOLD) rC <= C;
1319 if (!AHOLD) rA <= A;
1322 assign iC = C_REG ? rC : C;
1323 assign iA = A_REG ? rA : A;
1327 always @(posedge clock, posedge IRSTBOT) begin
1331 end else if (CE) begin
1332 if (!BHOLD) rB <= B;
1333 if (!DHOLD) rD <= D;
1336 assign iB = B_REG ? rB : B;
1337 assign iD = D_REG ? rD : D;
1340 wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
1341 wire [15:0] Ah, Al, Bh, Bl;
1342 assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]};
1343 assign Al = {A_SIGNED ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
1344 assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]};
1345 assign Bl = {B_SIGNED ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
1346 assign p_Ah_Bh = Ah * Bh;
1347 assign p_Al_Bh = Al * Bh;
1348 assign p_Ah_Bl = Ah * Bl;
1349 assign p_Al_Bl = Al * Bl;
1353 always @(posedge clock, posedge IRSTTOP) begin
1357 end else if (CE) begin
1359 if (!MODE_8x8) rJ <= p_Al_Bh;
1362 assign iF = TOP_8x8_MULT_REG ? rF : p_Ah_Bh;
1363 assign iJ = PIPELINE_16x16_MULT_REG1 ? rJ : p_Al_Bh;
1367 always @(posedge clock, posedge IRSTBOT) begin
1371 end else if (CE) begin
1372 if (!MODE_8x8) rK <= p_Ah_Bl;
1376 assign iK = PIPELINE_16x16_MULT_REG1 ? rK : p_Ah_Bl;
1377 assign iG = BOT_8x8_MULT_REG ? rG : p_Al_Bl;
1380 assign iL = iG + (iK << 8) + (iJ << 8) + (iF << 16);
1384 always @(posedge clock, posedge IRSTBOT) begin
1387 end else if (CE) begin
1388 if (!MODE_8x8) rH <= iL;
1391 assign iH = PIPELINE_16x16_MULT_REG2 ? rH : iL;
1396 assign iW = TOPADDSUB_UPPERINPUT ? iC : iQ;
1397 assign iX = (TOPADDSUB_LOWERINPUT == 0) ? iA : (TOPADDSUB_LOWERINPUT == 1) ? iF : (TOPADDSUB_LOWERINPUT == 2) ? iH[31:16] : {16{iZ[15]}};
1398 assign {ACCUMCO, XW} = iX + (iW ^ {16{ADDSUBTOP}}) + HCI;
1399 assign CO = ACCUMCO ^ ADDSUBTOP;
1400 assign iP = OLOADTOP ? iC : XW ^ {16{ADDSUBTOP}};
1401 always @(posedge clock, posedge ORSTTOP) begin
1404 end else if (CE) begin
1405 if (!OHOLDTOP) rQ <= iP;
1409 assign Oh = (TOPOUTPUT_SELECT == 0) ? iP : (TOPOUTPUT_SELECT == 1) ? iQ : (TOPOUTPUT_SELECT == 2) ? iF : iH[31:16];
1410 assign HCI = (TOPADDSUB_CARRYSELECT == 0) ? 1'b0 : (TOPADDSUB_CARRYSELECT == 1) ? 1'b1 : (TOPADDSUB_CARRYSELECT == 2) ? LCO : LCO ^ ADDSUBBOT;
1411 assign SIGNEXTOUT = iX[15];
1416 assign iY = BOTADDSUB_UPPERINPUT ? iD : iS;
1417 assign iZ = (BOTADDSUB_LOWERINPUT == 0) ? iB : (BOTADDSUB_LOWERINPUT == 1) ? iG : (BOTADDSUB_LOWERINPUT == 2) ? iH[15:0] : {16{SIGNEXTIN}};
1418 assign {LCO, YZ} = iZ + (iY ^ {16{ADDSUBBOT}}) + LCI;
1419 assign iR = OLOADBOT ? iD : YZ ^ {16{ADDSUBBOT}};
1420 always @(posedge clock, posedge ORSTBOT) begin
1423 end else if (CE) begin
1424 if (!OHOLDBOT) rS <= iR;
1428 assign Ol = (BOTOUTPUT_SELECT == 0) ? iR : (BOTOUTPUT_SELECT == 1) ? iS : (BOTOUTPUT_SELECT == 2) ? iG : iH[15:0];
1429 assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI;
1430 assign O = {Oh, Ol};