2 `define SB_DFF_REG reg Q = 0
3 // `define SB_DFF_REG reg Q
5 // SiliconBlue IO Cells
9 input LATCH_INPUT_VALUE,
19 parameter [5:0] PIN_TYPE = 6'b000000;
20 parameter [0:0] PULLUP = 1'b0;
21 parameter [0:0] NEG_TRIGGER = 1'b0;
22 parameter IO_STANDARD = "SB_LVCMOS";
25 reg dout, din_0, din_1;
27 reg dout_q_0, dout_q_1;
30 // IO tile generates a constant 1'b1 internally if global_cen is not connected
31 wire clken_pulled = CLOCK_ENABLE || CLOCK_ENABLE === 1'bz;
35 generate if (!NEG_TRIGGER) begin
36 always @(posedge INPUT_CLK) clken_pulled_ri <= clken_pulled;
37 always @(posedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN;
38 always @(negedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN;
39 always @(posedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled;
40 always @(posedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0;
41 always @(negedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1;
42 always @(posedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE;
44 always @(negedge INPUT_CLK) clken_pulled_ri <= clken_pulled;
45 always @(negedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN;
46 always @(posedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN;
47 always @(negedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled;
48 always @(negedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0;
49 always @(posedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1;
50 always @(negedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE;
54 if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
55 din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
59 // work around simulation glitches on dout in DDR mode
62 always @* outclk_delayed_1 <= OUTPUT_CLK;
63 always @* outclk_delayed_2 <= outclk_delayed_1;
67 dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
69 dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
72 assign D_IN_0 = din_0, D_IN_1 = din_1;
75 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
76 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
77 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
84 output GLOBAL_BUFFER_OUTPUT,
85 input LATCH_INPUT_VALUE,
95 parameter [5:0] PIN_TYPE = 6'b000000;
96 parameter [0:0] PULLUP = 1'b0;
97 parameter [0:0] NEG_TRIGGER = 1'b0;
98 parameter IO_STANDARD = "SB_LVCMOS";
100 assign GLOBAL_BUFFER_OUTPUT = PACKAGE_PIN;
105 .NEG_TRIGGER(NEG_TRIGGER),
106 .IO_STANDARD(IO_STANDARD)
108 .PACKAGE_PIN(PACKAGE_PIN),
109 .LATCH_INPUT_VALUE(LATCH_INPUT_VALUE),
110 .CLOCK_ENABLE(CLOCK_ENABLE),
111 .INPUT_CLK(INPUT_CLK),
112 .OUTPUT_CLK(OUTPUT_CLK),
113 .OUTPUT_ENABLE(OUTPUT_ENABLE),
122 input USER_SIGNAL_TO_GLOBAL_BUFFER,
123 output GLOBAL_BUFFER_OUTPUT
125 assign GLOBAL_BUFFER_OUTPUT = USER_SIGNAL_TO_GLOBAL_BUFFER;
128 // SiliconBlue Logic Cells
131 module SB_LUT4 (output O, input I0, I1, I2, I3);
132 parameter [15:0] LUT_INIT = 0;
133 wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
134 wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
135 wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];
136 assign O = I0 ? s1[1] : s1[0];
140 module SB_CARRY (output CO, input I0, I1, CI);
141 assign CO = (I0 && I1) || ((I0 || I1) && CI);
144 (* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
145 module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
153 // I0: 1010 1010 1010 1010
154 // I1: 1100 1100 1100 1100
155 // I2: 1111 0000 1111 0000
156 // I3: 1111 1111 0000 0000
157 .LUT_INIT(16'b 0110_1001_1001_0110)
167 // Positive Edge SiliconBlue FF Cells
169 module SB_DFF (output `SB_DFF_REG, input C, D);
174 module SB_DFFE (output `SB_DFF_REG, input C, E, D);
180 module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
188 module SB_DFFR (output `SB_DFF_REG, input C, R, D);
189 always @(posedge C, posedge R)
196 module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
204 module SB_DFFS (output `SB_DFF_REG, input C, S, D);
205 always @(posedge C, posedge S)
212 module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
222 module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
223 always @(posedge C, posedge R)
230 module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
240 module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
241 always @(posedge C, posedge S)
248 // Negative Edge SiliconBlue FF Cells
250 module SB_DFFN (output `SB_DFF_REG, input C, D);
255 module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
261 module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
269 module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
270 always @(negedge C, posedge R)
277 module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
285 module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
286 always @(negedge C, posedge S)
293 module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
303 module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
304 always @(negedge C, posedge R)
311 module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
321 module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
322 always @(negedge C, posedge S)
329 // SiliconBlue RAM Cells
333 input RCLK, RCLKE, RE,
335 input WCLK, WCLKE, WE,
337 input [15:0] MASK, WDATA
343 parameter WRITE_MODE = 0;
344 parameter READ_MODE = 0;
346 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
347 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
348 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
349 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
350 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
351 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
352 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
353 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
354 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
355 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
356 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
357 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
358 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
359 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
360 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
361 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
363 parameter INIT_FILE = "";
374 0: assign WMASK_I = MASK;
376 1: assign WMASK_I = WADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
377 WADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
379 2: assign WMASK_I = WADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
380 WADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
381 WADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
382 WADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
384 3: assign WMASK_I = WADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
385 WADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
386 WADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
387 WADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
388 WADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
389 WADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
390 WADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
391 WADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
395 0: assign RMASK_I = 16'b 0000_0000_0000_0000;
397 1: assign RMASK_I = RADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
398 RADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
400 2: assign RMASK_I = RADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
401 RADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
402 RADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
403 RADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
405 3: assign RMASK_I = RADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
406 RADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
407 RADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
408 RADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
409 RADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
410 RADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
411 RADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
412 RADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
416 0: assign WDATA_I = WDATA;
418 1: assign WDATA_I = {WDATA[14], WDATA[14], WDATA[12], WDATA[12],
419 WDATA[10], WDATA[10], WDATA[ 8], WDATA[ 8],
420 WDATA[ 6], WDATA[ 6], WDATA[ 4], WDATA[ 4],
421 WDATA[ 2], WDATA[ 2], WDATA[ 0], WDATA[ 0]};
423 2: assign WDATA_I = {WDATA[13], WDATA[13], WDATA[13], WDATA[13],
424 WDATA[ 9], WDATA[ 9], WDATA[ 9], WDATA[ 9],
425 WDATA[ 5], WDATA[ 5], WDATA[ 5], WDATA[ 5],
426 WDATA[ 1], WDATA[ 1], WDATA[ 1], WDATA[ 1]};
428 3: assign WDATA_I = {WDATA[11], WDATA[11], WDATA[11], WDATA[11],
429 WDATA[11], WDATA[11], WDATA[11], WDATA[11],
430 WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3],
431 WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3]};
435 0: assign RDATA = RDATA_I;
436 1: assign RDATA = {1'b0, |RDATA_I[15:14], 1'b0, |RDATA_I[13:12], 1'b0, |RDATA_I[11:10], 1'b0, |RDATA_I[ 9: 8],
437 1'b0, |RDATA_I[ 7: 6], 1'b0, |RDATA_I[ 5: 4], 1'b0, |RDATA_I[ 3: 2], 1'b0, |RDATA_I[ 1: 0]};
438 2: assign RDATA = {2'b0, |RDATA_I[15:12], 3'b0, |RDATA_I[11: 8], 3'b0, |RDATA_I[ 7: 4], 3'b0, |RDATA_I[ 3: 0], 1'b0};
439 3: assign RDATA = {4'b0, |RDATA_I[15: 8], 7'b0, |RDATA_I[ 7: 0], 3'b0};
444 reg [15:0] memory [0:255];
448 $readmemh(INIT_FILE, memory);
450 for (i=0; i<16; i=i+1) begin
451 memory[ 0*16 + i] = INIT_0[16*i +: 16];
452 memory[ 1*16 + i] = INIT_1[16*i +: 16];
453 memory[ 2*16 + i] = INIT_2[16*i +: 16];
454 memory[ 3*16 + i] = INIT_3[16*i +: 16];
455 memory[ 4*16 + i] = INIT_4[16*i +: 16];
456 memory[ 5*16 + i] = INIT_5[16*i +: 16];
457 memory[ 6*16 + i] = INIT_6[16*i +: 16];
458 memory[ 7*16 + i] = INIT_7[16*i +: 16];
459 memory[ 8*16 + i] = INIT_8[16*i +: 16];
460 memory[ 9*16 + i] = INIT_9[16*i +: 16];
461 memory[10*16 + i] = INIT_A[16*i +: 16];
462 memory[11*16 + i] = INIT_B[16*i +: 16];
463 memory[12*16 + i] = INIT_C[16*i +: 16];
464 memory[13*16 + i] = INIT_D[16*i +: 16];
465 memory[14*16 + i] = INIT_E[16*i +: 16];
466 memory[15*16 + i] = INIT_F[16*i +: 16];
470 always @(posedge WCLK) begin
471 if (WE && WCLKE) begin
472 if (!WMASK_I[ 0]) memory[WADDR[7:0]][ 0] <= WDATA_I[ 0];
473 if (!WMASK_I[ 1]) memory[WADDR[7:0]][ 1] <= WDATA_I[ 1];
474 if (!WMASK_I[ 2]) memory[WADDR[7:0]][ 2] <= WDATA_I[ 2];
475 if (!WMASK_I[ 3]) memory[WADDR[7:0]][ 3] <= WDATA_I[ 3];
476 if (!WMASK_I[ 4]) memory[WADDR[7:0]][ 4] <= WDATA_I[ 4];
477 if (!WMASK_I[ 5]) memory[WADDR[7:0]][ 5] <= WDATA_I[ 5];
478 if (!WMASK_I[ 6]) memory[WADDR[7:0]][ 6] <= WDATA_I[ 6];
479 if (!WMASK_I[ 7]) memory[WADDR[7:0]][ 7] <= WDATA_I[ 7];
480 if (!WMASK_I[ 8]) memory[WADDR[7:0]][ 8] <= WDATA_I[ 8];
481 if (!WMASK_I[ 9]) memory[WADDR[7:0]][ 9] <= WDATA_I[ 9];
482 if (!WMASK_I[10]) memory[WADDR[7:0]][10] <= WDATA_I[10];
483 if (!WMASK_I[11]) memory[WADDR[7:0]][11] <= WDATA_I[11];
484 if (!WMASK_I[12]) memory[WADDR[7:0]][12] <= WDATA_I[12];
485 if (!WMASK_I[13]) memory[WADDR[7:0]][13] <= WDATA_I[13];
486 if (!WMASK_I[14]) memory[WADDR[7:0]][14] <= WDATA_I[14];
487 if (!WMASK_I[15]) memory[WADDR[7:0]][15] <= WDATA_I[15];
491 always @(posedge RCLK) begin
492 if (RE && RCLKE) begin
493 RDATA_I <= memory[RADDR[7:0]] & ~RMASK_I;
499 module SB_RAM40_4KNR (
501 input RCLKN, RCLKE, RE,
503 input WCLK, WCLKE, WE,
505 input [15:0] MASK, WDATA
507 parameter WRITE_MODE = 0;
508 parameter READ_MODE = 0;
510 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
511 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
512 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
513 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
514 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
515 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
516 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
517 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
518 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
519 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
520 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
521 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
522 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
523 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
524 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
525 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
527 parameter INIT_FILE = "";
530 .WRITE_MODE(WRITE_MODE),
531 .READ_MODE (READ_MODE ),
548 .INIT_FILE (INIT_FILE )
564 module SB_RAM40_4KNW (
566 input RCLK, RCLKE, RE,
568 input WCLKN, WCLKE, WE,
570 input [15:0] MASK, WDATA
572 parameter WRITE_MODE = 0;
573 parameter READ_MODE = 0;
575 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
576 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
577 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
578 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
579 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
580 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
581 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
582 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
583 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
584 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
585 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
586 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
587 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
588 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
589 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
590 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
592 parameter INIT_FILE = "";
595 .WRITE_MODE(WRITE_MODE),
596 .READ_MODE (READ_MODE ),
613 .INIT_FILE (INIT_FILE )
629 module SB_RAM40_4KNRNW (
631 input RCLKN, RCLKE, RE,
633 input WCLKN, WCLKE, WE,
635 input [15:0] MASK, WDATA
637 parameter WRITE_MODE = 0;
638 parameter READ_MODE = 0;
640 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
641 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
642 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
643 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
644 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
645 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
646 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
647 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
648 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
649 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
650 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
651 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
652 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
653 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
654 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
655 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
657 parameter INIT_FILE = "";
660 .WRITE_MODE(WRITE_MODE),
661 .READ_MODE (READ_MODE ),
678 .INIT_FILE (INIT_FILE )
694 // Packed IceStorm Logic Cells
697 input I0, I1, I2, I3, CIN, CLK, CEN, SR,
700 parameter [15:0] LUT_INIT = 0;
702 parameter [0:0] NEG_CLK = 0;
703 parameter [0:0] CARRY_ENABLE = 0;
704 parameter [0:0] DFF_ENABLE = 0;
705 parameter [0:0] SET_NORESET = 0;
706 parameter [0:0] ASYNC_SR = 0;
708 parameter [0:0] CIN_CONST = 0;
709 parameter [0:0] CIN_SET = 0;
711 wire mux_cin = CIN_CONST ? CIN_SET : CIN;
713 assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && mux_cin) : 1'bx;
715 wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
716 wire [3:0] lut_s2 = I2 ? lut_s3[ 7:4] : lut_s3[3:0];
717 wire [1:0] lut_s1 = I1 ? lut_s2[ 3:2] : lut_s2[1:0];
718 wire lut_o = I0 ? lut_s1[ 1] : lut_s1[ 0];
723 assign polarized_clk = CLK ^ NEG_CLK;
726 always @(posedge polarized_clk)
728 o_reg <= SR ? SET_NORESET : lut_o;
731 always @(posedge polarized_clk, posedge SR)
733 o_reg <= SET_NORESET;
737 assign O = DFF_ENABLE ? ASYNC_SR ? o_reg_async : o_reg : lut_o;
740 // SiliconBlue PLL Cells
743 module SB_PLL40_CORE (
748 input [7:0] DYNAMICDELAY,
752 input LATCHINPUTVALUE,
757 parameter FEEDBACK_PATH = "SIMPLE";
758 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
759 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
760 parameter SHIFTREG_DIV_MODE = 1'b0;
761 parameter FDA_FEEDBACK = 4'b0000;
762 parameter FDA_RELATIVE = 4'b0000;
763 parameter PLLOUT_SELECT = "GENCLK";
764 parameter DIVR = 4'b0000;
765 parameter DIVF = 7'b0000000;
766 parameter DIVQ = 3'b000;
767 parameter FILTER_RANGE = 3'b000;
768 parameter ENABLE_ICEGATE = 1'b0;
769 parameter TEST_MODE = 1'b0;
770 parameter EXTERNAL_DIVIDE_FACTOR = 1;
774 module SB_PLL40_PAD (
779 input [7:0] DYNAMICDELAY,
783 input LATCHINPUTVALUE,
788 parameter FEEDBACK_PATH = "SIMPLE";
789 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
790 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
791 parameter SHIFTREG_DIV_MODE = 1'b0;
792 parameter FDA_FEEDBACK = 4'b0000;
793 parameter FDA_RELATIVE = 4'b0000;
794 parameter PLLOUT_SELECT = "GENCLK";
795 parameter DIVR = 4'b0000;
796 parameter DIVF = 7'b0000000;
797 parameter DIVQ = 3'b000;
798 parameter FILTER_RANGE = 3'b000;
799 parameter ENABLE_ICEGATE = 1'b0;
800 parameter TEST_MODE = 1'b0;
801 parameter EXTERNAL_DIVIDE_FACTOR = 1;
805 module SB_PLL40_2_PAD (
808 output PLLOUTGLOBALA,
810 output PLLOUTGLOBALB,
812 input [7:0] DYNAMICDELAY,
816 input LATCHINPUTVALUE,
821 parameter FEEDBACK_PATH = "SIMPLE";
822 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
823 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
824 parameter SHIFTREG_DIV_MODE = 1'b0;
825 parameter FDA_FEEDBACK = 4'b0000;
826 parameter FDA_RELATIVE = 4'b0000;
827 parameter PLLOUT_SELECT_PORTB = "GENCLK";
828 parameter DIVR = 4'b0000;
829 parameter DIVF = 7'b0000000;
830 parameter DIVQ = 3'b000;
831 parameter FILTER_RANGE = 3'b000;
832 parameter ENABLE_ICEGATE_PORTA = 1'b0;
833 parameter ENABLE_ICEGATE_PORTB = 1'b0;
834 parameter TEST_MODE = 1'b0;
835 parameter EXTERNAL_DIVIDE_FACTOR = 1;
839 module SB_PLL40_2F_CORE (
842 output PLLOUTGLOBALA,
844 output PLLOUTGLOBALB,
846 input [7:0] DYNAMICDELAY,
850 input LATCHINPUTVALUE,
855 parameter FEEDBACK_PATH = "SIMPLE";
856 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
857 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
858 parameter SHIFTREG_DIV_MODE = 1'b0;
859 parameter FDA_FEEDBACK = 4'b0000;
860 parameter FDA_RELATIVE = 4'b0000;
861 parameter PLLOUT_SELECT_PORTA = "GENCLK";
862 parameter PLLOUT_SELECT_PORTB = "GENCLK";
863 parameter DIVR = 4'b0000;
864 parameter DIVF = 7'b0000000;
865 parameter DIVQ = 3'b000;
866 parameter FILTER_RANGE = 3'b000;
867 parameter ENABLE_ICEGATE_PORTA = 1'b0;
868 parameter ENABLE_ICEGATE_PORTB = 1'b0;
869 parameter TEST_MODE = 1'b0;
870 parameter EXTERNAL_DIVIDE_FACTOR = 1;
874 module SB_PLL40_2F_PAD (
877 output PLLOUTGLOBALA,
879 output PLLOUTGLOBALB,
881 input [7:0] DYNAMICDELAY,
885 input LATCHINPUTVALUE,
890 parameter FEEDBACK_PATH = "SIMPLE";
891 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
892 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
893 parameter SHIFTREG_DIV_MODE = 2'b00;
894 parameter FDA_FEEDBACK = 4'b0000;
895 parameter FDA_RELATIVE = 4'b0000;
896 parameter PLLOUT_SELECT_PORTA = "GENCLK";
897 parameter PLLOUT_SELECT_PORTB = "GENCLK";
898 parameter DIVR = 4'b0000;
899 parameter DIVF = 7'b0000000;
900 parameter DIVQ = 3'b000;
901 parameter FILTER_RANGE = 3'b000;
902 parameter ENABLE_ICEGATE_PORTA = 1'b0;
903 parameter ENABLE_ICEGATE_PORTB = 1'b0;
904 parameter TEST_MODE = 1'b0;
905 parameter EXTERNAL_DIVIDE_FACTOR = 1;
908 // SiliconBlue Device Configuration Cells
918 module SB_SPRAM256KA (
919 input [13:0] ADDRESS,
921 input [3:0] MASKWREN,
922 input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
923 output reg [15:0] DATAOUT
927 reg [15:0] mem [0:16383];
928 wire off = SLEEP || !POWEROFF;
931 always @(negedge POWEROFF) begin
932 for (i = 0; i <= 16383; i = i+1)
936 always @(posedge CLOCK, posedge off) begin
940 if (CHIPSELECT && !STANDBY && !WREN) begin
941 DATAOUT <= mem[ADDRESS];
943 if (CHIPSELECT && !STANDBY && WREN) begin
944 if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0];
945 if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4];
946 if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8];
947 if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12];
972 parameter TRIM_EN = "0b0";
973 parameter CLKHF_DIV = "0b00";
995 parameter CURRENT_MODE = "0b0";
996 parameter RGB0_CURRENT = "0b000000";
997 parameter RGB1_CURRENT = "0b000000";
998 parameter RGB2_CURRENT = "0b000000";
1002 module SB_LED_DRV_CUR(
1019 parameter CURRENT_MODE = "0b0";
1020 parameter RGB0_CURRENT = "0b000000";
1021 parameter RGB1_CURRENT = "0b000000";
1022 parameter RGB2_CURRENT = "0b000000";
1059 output SCLO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
1064 parameter I2C_SLAVE_INIT_ADDR = "0b1111100001";
1065 parameter BUS_ADDR74 = "0b0001";
1108 output SCKO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
1119 parameter BUS_ADDR74 = "0b0000";
1149 module SB_FILTER_50NS(
1157 input LATCH_INPUT_VALUE,
1161 input OUTPUT_ENABLE,
1169 parameter [5:0] PIN_TYPE = 6'b000000;
1170 parameter [0:0] PULLUP = 1'b0;
1171 parameter [0:0] WEAK_PULLUP = 1'b0;
1172 parameter [0:0] NEG_TRIGGER = 1'b0;
1173 parameter IO_STANDARD = "SB_LVCMOS";
1176 reg dout, din_0, din_1;
1177 reg din_q_0, din_q_1;
1178 reg dout_q_0, dout_q_1;
1181 generate if (!NEG_TRIGGER) begin
1182 always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
1183 always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
1184 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
1185 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
1186 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
1188 always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
1189 always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
1190 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
1191 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
1192 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
1196 if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
1197 din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
1201 // work around simulation glitches on dout in DDR mode
1202 reg outclk_delayed_1;
1203 reg outclk_delayed_2;
1204 always @* outclk_delayed_1 <= OUTPUT_CLK;
1205 always @* outclk_delayed_2 <= outclk_delayed_1;
1209 dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
1211 dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
1214 assign D_IN_0 = din_0, D_IN_1 = din_1;
1217 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
1218 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
1219 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
1226 input LATCHINPUTVALUE,
1236 parameter [5:0] PIN_TYPE = 6'b000000;
1237 parameter [0:0] NEG_TRIGGER = 1'b0;
1240 reg dout, din_0, din_1;
1241 reg din_q_0, din_q_1;
1242 reg dout_q_0, dout_q_1;
1245 generate if (!NEG_TRIGGER) begin
1246 always @(posedge INPUTCLK) if (CLOCKENABLE) din_q_0 <= PACKAGEPIN;
1247 always @(negedge INPUTCLK) if (CLOCKENABLE) din_q_1 <= PACKAGEPIN;
1248 always @(posedge OUTPUTCLK) if (CLOCKENABLE) dout_q_0 <= DOUT0;
1249 always @(negedge OUTPUTCLK) if (CLOCKENABLE) dout_q_1 <= DOUT1;
1250 always @(posedge OUTPUTCLK) if (CLOCKENABLE) outena_q <= OUTPUTENABLE;
1252 always @(negedge INPUTCLK) if (CLOCKENABLE) din_q_0 <= PACKAGEPIN;
1253 always @(posedge INPUTCLK) if (CLOCKENABLE) din_q_1 <= PACKAGEPIN;
1254 always @(negedge OUTPUTCLK) if (CLOCKENABLE) dout_q_0 <= DOUT0;
1255 always @(posedge OUTPUTCLK) if (CLOCKENABLE) dout_q_1 <= DOUT1;
1256 always @(negedge OUTPUTCLK) if (CLOCKENABLE) outena_q <= OUTPUTENABLE;
1260 if (!PIN_TYPE[1] || !LATCHINPUTVALUE)
1261 din_0 = PIN_TYPE[0] ? PACKAGEPIN : din_q_0;
1265 // work around simulation glitches on dout in DDR mode
1266 reg outclk_delayed_1;
1267 reg outclk_delayed_2;
1268 always @* outclk_delayed_1 <= OUTPUTCLK;
1269 always @* outclk_delayed_2 <= outclk_delayed_1;
1273 dout = PIN_TYPE[2] ? !dout_q_0 : DOUT0;
1275 dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
1278 assign DIN0 = din_0, DIN1 = din_1;
1281 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGEPIN = dout ? 1'bz : 1'b0;
1282 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGEPIN = OUTPUTENABLE ? (dout ? 1'bz : 1'b0) : 1'bz;
1283 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGEPIN = outena_q ? (dout ? 1'bz : 1'b0) : 1'bz;
1290 input [15:0] C, A, B, D,
1291 input AHOLD, BHOLD, CHOLD, DHOLD,
1292 input IRSTTOP, IRSTBOT,
1293 input ORSTTOP, ORSTBOT,
1294 input OLOADTOP, OLOADBOT,
1295 input ADDSUBTOP, ADDSUBBOT,
1296 input OHOLDTOP, OHOLDBOT,
1297 input CI, ACCUMCI, SIGNEXTIN,
1299 output CO, ACCUMCO, SIGNEXTOUT
1301 parameter [0:0] NEG_TRIGGER = 0;
1302 parameter [0:0] C_REG = 0;
1303 parameter [0:0] A_REG = 0;
1304 parameter [0:0] B_REG = 0;
1305 parameter [0:0] D_REG = 0;
1306 parameter [0:0] TOP_8x8_MULT_REG = 0;
1307 parameter [0:0] BOT_8x8_MULT_REG = 0;
1308 parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
1309 parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
1310 parameter [1:0] TOPOUTPUT_SELECT = 0;
1311 parameter [1:0] TOPADDSUB_LOWERINPUT = 0;
1312 parameter [0:0] TOPADDSUB_UPPERINPUT = 0;
1313 parameter [1:0] TOPADDSUB_CARRYSELECT = 0;
1314 parameter [1:0] BOTOUTPUT_SELECT = 0;
1315 parameter [1:0] BOTADDSUB_LOWERINPUT = 0;
1316 parameter [0:0] BOTADDSUB_UPPERINPUT = 0;
1317 parameter [1:0] BOTADDSUB_CARRYSELECT = 0;
1318 parameter [0:0] MODE_8x8 = 0;
1319 parameter [0:0] A_SIGNED = 0;
1320 parameter [0:0] B_SIGNED = 0;
1322 wire clock = CLK ^ NEG_TRIGGER;
1324 // internal wires, compare Figure on page 133 of ICE Technology Library 3.0 and Fig 2 on page 2 of Lattice TN1295-DSP
1325 // http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201608.pdf
1326 // https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/AD/DSPFunctionUsageGuideforICE40Devices.ashx
1327 wire [15:0] iA, iB, iC, iD;
1328 wire [15:0] iF, iJ, iK, iG;
1330 wire [15:0] iW, iX, iP, iQ;
1331 wire [15:0] iY, iZ, iR, iS;
1336 always @(posedge clock, posedge IRSTTOP) begin
1340 end else if (CE) begin
1341 if (!CHOLD) rC <= C;
1342 if (!AHOLD) rA <= A;
1345 assign iC = C_REG ? rC : C;
1346 assign iA = A_REG ? rA : A;
1350 always @(posedge clock, posedge IRSTBOT) begin
1354 end else if (CE) begin
1355 if (!BHOLD) rB <= B;
1356 if (!DHOLD) rD <= D;
1359 assign iB = B_REG ? rB : B;
1360 assign iD = D_REG ? rD : D;
1363 wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
1364 wire [15:0] Ah, Al, Bh, Bl;
1365 assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]};
1366 assign Al = {A_SIGNED ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
1367 assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]};
1368 assign Bl = {B_SIGNED ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
1369 assign p_Ah_Bh = Ah * Bh;
1370 assign p_Al_Bh = Al * Bh;
1371 assign p_Ah_Bl = Ah * Bl;
1372 assign p_Al_Bl = Al * Bl;
1376 always @(posedge clock, posedge IRSTTOP) begin
1380 end else if (CE) begin
1382 if (!MODE_8x8) rJ <= p_Al_Bh;
1385 assign iF = TOP_8x8_MULT_REG ? rF : p_Ah_Bh;
1386 assign iJ = PIPELINE_16x16_MULT_REG1 ? rJ : p_Al_Bh;
1390 always @(posedge clock, posedge IRSTBOT) begin
1394 end else if (CE) begin
1395 if (!MODE_8x8) rK <= p_Ah_Bl;
1399 assign iK = PIPELINE_16x16_MULT_REG1 ? rK : p_Ah_Bl;
1400 assign iG = BOT_8x8_MULT_REG ? rG : p_Al_Bl;
1403 assign iL = iG + (iK << 8) + (iJ << 8) + (iF << 16);
1407 always @(posedge clock, posedge IRSTBOT) begin
1410 end else if (CE) begin
1411 if (!MODE_8x8) rH <= iL;
1414 assign iH = PIPELINE_16x16_MULT_REG2 ? rH : iL;
1419 assign iW = TOPADDSUB_UPPERINPUT ? iC : iQ;
1420 assign iX = (TOPADDSUB_LOWERINPUT == 0) ? iA : (TOPADDSUB_LOWERINPUT == 1) ? iF : (TOPADDSUB_LOWERINPUT == 2) ? iH[31:16] : {16{iZ[15]}};
1421 assign {ACCUMCO, XW} = iX + (iW ^ {16{ADDSUBTOP}}) + HCI;
1422 assign CO = ACCUMCO ^ ADDSUBTOP;
1423 assign iP = OLOADTOP ? iC : XW ^ {16{ADDSUBTOP}};
1424 always @(posedge clock, posedge ORSTTOP) begin
1427 end else if (CE) begin
1428 if (!OHOLDTOP) rQ <= iP;
1432 assign Oh = (TOPOUTPUT_SELECT == 0) ? iP : (TOPOUTPUT_SELECT == 1) ? iQ : (TOPOUTPUT_SELECT == 2) ? iF : iH[31:16];
1433 assign HCI = (TOPADDSUB_CARRYSELECT == 0) ? 1'b0 : (TOPADDSUB_CARRYSELECT == 1) ? 1'b1 : (TOPADDSUB_CARRYSELECT == 2) ? LCO : LCO ^ ADDSUBBOT;
1434 assign SIGNEXTOUT = iX[15];
1439 assign iY = BOTADDSUB_UPPERINPUT ? iD : iS;
1440 assign iZ = (BOTADDSUB_LOWERINPUT == 0) ? iB : (BOTADDSUB_LOWERINPUT == 1) ? iG : (BOTADDSUB_LOWERINPUT == 2) ? iH[15:0] : {16{SIGNEXTIN}};
1441 assign {LCO, YZ} = iZ + (iY ^ {16{ADDSUBBOT}}) + LCI;
1442 assign iR = OLOADBOT ? iD : YZ ^ {16{ADDSUBBOT}};
1443 always @(posedge clock, posedge ORSTBOT) begin
1446 end else if (CE) begin
1447 if (!OHOLDBOT) rS <= iR;
1451 assign Ol = (BOTOUTPUT_SELECT == 0) ? iR : (BOTOUTPUT_SELECT == 1) ? iS : (BOTOUTPUT_SELECT == 2) ? iG : iH[15:0];
1452 assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI;
1453 assign O = {Oh, Ol};