2 `define SB_DFF_REG reg Q = 0
3 // `define SB_DFF_REG reg Q
5 // SiliconBlue IO Cells
9 input LATCH_INPUT_VALUE,
19 parameter [5:0] PIN_TYPE = 6'b000000;
20 parameter [0:0] PULLUP = 1'b0;
21 parameter [0:0] NEG_TRIGGER = 1'b0;
22 parameter IO_STANDARD = "SB_LVCMOS";
25 reg dout, din_0, din_1;
27 reg dout_q_0, dout_q_1;
30 // IO tile generates a constant 1'b1 internally if global_cen is not connected
31 wire clken_pulled = CLOCK_ENABLE || CLOCK_ENABLE === 1'bz;
35 generate if (!NEG_TRIGGER) begin
36 always @(posedge INPUT_CLK) clken_pulled_ri <= clken_pulled;
37 always @(posedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN;
38 always @(negedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN;
39 always @(posedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled;
40 always @(posedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0;
41 always @(negedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1;
42 always @(posedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE;
44 always @(negedge INPUT_CLK) clken_pulled_ri <= clken_pulled;
45 always @(negedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN;
46 always @(posedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN;
47 always @(negedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled;
48 always @(negedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0;
49 always @(posedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1;
50 always @(negedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE;
54 if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
55 din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
59 // work around simulation glitches on dout in DDR mode
62 always @* outclk_delayed_1 <= OUTPUT_CLK;
63 always @* outclk_delayed_2 <= outclk_delayed_1;
67 dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
69 dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
72 assign D_IN_0 = din_0, D_IN_1 = din_1;
75 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
76 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
77 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
84 output GLOBAL_BUFFER_OUTPUT,
85 input LATCH_INPUT_VALUE,
95 parameter [5:0] PIN_TYPE = 6'b000000;
96 parameter [0:0] PULLUP = 1'b0;
97 parameter [0:0] NEG_TRIGGER = 1'b0;
98 parameter IO_STANDARD = "SB_LVCMOS";
100 assign GLOBAL_BUFFER_OUTPUT = PACKAGE_PIN;
105 .NEG_TRIGGER(NEG_TRIGGER),
106 .IO_STANDARD(IO_STANDARD)
108 .PACKAGE_PIN(PACKAGE_PIN),
109 .LATCH_INPUT_VALUE(LATCH_INPUT_VALUE),
110 .CLOCK_ENABLE(CLOCK_ENABLE),
111 .INPUT_CLK(INPUT_CLK),
112 .OUTPUT_CLK(OUTPUT_CLK),
113 .OUTPUT_ENABLE(OUTPUT_ENABLE),
122 input USER_SIGNAL_TO_GLOBAL_BUFFER,
123 output GLOBAL_BUFFER_OUTPUT
125 assign GLOBAL_BUFFER_OUTPUT = USER_SIGNAL_TO_GLOBAL_BUFFER;
128 // SiliconBlue Logic Cells
130 (* abc_box_id = 2, lib_whitebox *)
131 module SB_LUT4 (output O, input I0, I1, I2, I3);
132 parameter [15:0] LUT_INIT = 0;
133 wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
134 wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
135 wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];
136 assign O = I0 ? s1[1] : s1[0];
139 (* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
140 module SB_CARRY (output CO, input I0, I1, CI);
141 assign CO = (I0 && I1) || ((I0 || I1) && CI);
144 // Positive Edge SiliconBlue FF Cells
146 module SB_DFF (output `SB_DFF_REG, input C, D);
155 module SB_DFFE (output `SB_DFF_REG, input C, E, D);
161 module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
169 module SB_DFFR (output `SB_DFF_REG, input C, R, D);
170 always @(posedge C, posedge R)
177 module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
185 module SB_DFFS (output `SB_DFF_REG, input C, S, D);
186 always @(posedge C, posedge S)
193 module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
203 module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
204 always @(posedge C, posedge R)
211 module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
221 module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
222 always @(posedge C, posedge S)
229 // Negative Edge SiliconBlue FF Cells
231 module SB_DFFN (output `SB_DFF_REG, input C, D);
236 module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
242 module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
250 module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
251 always @(negedge C, posedge R)
258 module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
266 module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
267 always @(negedge C, posedge S)
274 module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
284 module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
285 always @(negedge C, posedge R)
292 module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
302 module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
303 always @(negedge C, posedge S)
310 // SiliconBlue RAM Cells
314 input RCLK, RCLKE, RE,
316 input WCLK, WCLKE, WE,
318 input [15:0] MASK, WDATA
324 parameter WRITE_MODE = 0;
325 parameter READ_MODE = 0;
327 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
328 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
329 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
330 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
331 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
332 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
333 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
334 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
335 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
336 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
337 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
338 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
339 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
340 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
341 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
342 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
344 parameter INIT_FILE = "";
355 0: assign WMASK_I = MASK;
357 1: assign WMASK_I = WADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
358 WADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
360 2: assign WMASK_I = WADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
361 WADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
362 WADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
363 WADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
365 3: assign WMASK_I = WADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
366 WADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
367 WADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
368 WADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
369 WADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
370 WADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
371 WADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
372 WADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
376 0: assign RMASK_I = 16'b 0000_0000_0000_0000;
378 1: assign RMASK_I = RADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
379 RADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
381 2: assign RMASK_I = RADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
382 RADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
383 RADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
384 RADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
386 3: assign RMASK_I = RADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
387 RADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
388 RADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
389 RADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
390 RADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
391 RADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
392 RADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
393 RADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
397 0: assign WDATA_I = WDATA;
399 1: assign WDATA_I = {WDATA[14], WDATA[14], WDATA[12], WDATA[12],
400 WDATA[10], WDATA[10], WDATA[ 8], WDATA[ 8],
401 WDATA[ 6], WDATA[ 6], WDATA[ 4], WDATA[ 4],
402 WDATA[ 2], WDATA[ 2], WDATA[ 0], WDATA[ 0]};
404 2: assign WDATA_I = {WDATA[13], WDATA[13], WDATA[13], WDATA[13],
405 WDATA[ 9], WDATA[ 9], WDATA[ 9], WDATA[ 9],
406 WDATA[ 5], WDATA[ 5], WDATA[ 5], WDATA[ 5],
407 WDATA[ 1], WDATA[ 1], WDATA[ 1], WDATA[ 1]};
409 3: assign WDATA_I = {WDATA[11], WDATA[11], WDATA[11], WDATA[11],
410 WDATA[11], WDATA[11], WDATA[11], WDATA[11],
411 WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3],
412 WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3]};
416 0: assign RDATA = RDATA_I;
417 1: assign RDATA = {1'b0, |RDATA_I[15:14], 1'b0, |RDATA_I[13:12], 1'b0, |RDATA_I[11:10], 1'b0, |RDATA_I[ 9: 8],
418 1'b0, |RDATA_I[ 7: 6], 1'b0, |RDATA_I[ 5: 4], 1'b0, |RDATA_I[ 3: 2], 1'b0, |RDATA_I[ 1: 0]};
419 2: assign RDATA = {2'b0, |RDATA_I[15:12], 3'b0, |RDATA_I[11: 8], 3'b0, |RDATA_I[ 7: 4], 3'b0, |RDATA_I[ 3: 0], 1'b0};
420 3: assign RDATA = {4'b0, |RDATA_I[15: 8], 7'b0, |RDATA_I[ 7: 0], 3'b0};
425 reg [15:0] memory [0:255];
429 $readmemh(INIT_FILE, memory);
431 for (i=0; i<16; i=i+1) begin
432 memory[ 0*16 + i] = INIT_0[16*i +: 16];
433 memory[ 1*16 + i] = INIT_1[16*i +: 16];
434 memory[ 2*16 + i] = INIT_2[16*i +: 16];
435 memory[ 3*16 + i] = INIT_3[16*i +: 16];
436 memory[ 4*16 + i] = INIT_4[16*i +: 16];
437 memory[ 5*16 + i] = INIT_5[16*i +: 16];
438 memory[ 6*16 + i] = INIT_6[16*i +: 16];
439 memory[ 7*16 + i] = INIT_7[16*i +: 16];
440 memory[ 8*16 + i] = INIT_8[16*i +: 16];
441 memory[ 9*16 + i] = INIT_9[16*i +: 16];
442 memory[10*16 + i] = INIT_A[16*i +: 16];
443 memory[11*16 + i] = INIT_B[16*i +: 16];
444 memory[12*16 + i] = INIT_C[16*i +: 16];
445 memory[13*16 + i] = INIT_D[16*i +: 16];
446 memory[14*16 + i] = INIT_E[16*i +: 16];
447 memory[15*16 + i] = INIT_F[16*i +: 16];
451 always @(posedge WCLK) begin
452 if (WE && WCLKE) begin
453 if (!WMASK_I[ 0]) memory[WADDR[7:0]][ 0] <= WDATA_I[ 0];
454 if (!WMASK_I[ 1]) memory[WADDR[7:0]][ 1] <= WDATA_I[ 1];
455 if (!WMASK_I[ 2]) memory[WADDR[7:0]][ 2] <= WDATA_I[ 2];
456 if (!WMASK_I[ 3]) memory[WADDR[7:0]][ 3] <= WDATA_I[ 3];
457 if (!WMASK_I[ 4]) memory[WADDR[7:0]][ 4] <= WDATA_I[ 4];
458 if (!WMASK_I[ 5]) memory[WADDR[7:0]][ 5] <= WDATA_I[ 5];
459 if (!WMASK_I[ 6]) memory[WADDR[7:0]][ 6] <= WDATA_I[ 6];
460 if (!WMASK_I[ 7]) memory[WADDR[7:0]][ 7] <= WDATA_I[ 7];
461 if (!WMASK_I[ 8]) memory[WADDR[7:0]][ 8] <= WDATA_I[ 8];
462 if (!WMASK_I[ 9]) memory[WADDR[7:0]][ 9] <= WDATA_I[ 9];
463 if (!WMASK_I[10]) memory[WADDR[7:0]][10] <= WDATA_I[10];
464 if (!WMASK_I[11]) memory[WADDR[7:0]][11] <= WDATA_I[11];
465 if (!WMASK_I[12]) memory[WADDR[7:0]][12] <= WDATA_I[12];
466 if (!WMASK_I[13]) memory[WADDR[7:0]][13] <= WDATA_I[13];
467 if (!WMASK_I[14]) memory[WADDR[7:0]][14] <= WDATA_I[14];
468 if (!WMASK_I[15]) memory[WADDR[7:0]][15] <= WDATA_I[15];
472 always @(posedge RCLK) begin
473 if (RE && RCLKE) begin
474 RDATA_I <= memory[RADDR[7:0]] & ~RMASK_I;
480 module SB_RAM40_4KNR (
482 input RCLKN, RCLKE, RE,
484 input WCLK, WCLKE, WE,
486 input [15:0] MASK, WDATA
488 parameter WRITE_MODE = 0;
489 parameter READ_MODE = 0;
491 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
492 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
493 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
494 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
495 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
496 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
497 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
498 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
499 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
500 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
501 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
502 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
503 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
504 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
505 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
506 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
508 parameter INIT_FILE = "";
511 .WRITE_MODE(WRITE_MODE),
512 .READ_MODE (READ_MODE ),
529 .INIT_FILE (INIT_FILE )
545 module SB_RAM40_4KNW (
547 input RCLK, RCLKE, RE,
549 input WCLKN, WCLKE, WE,
551 input [15:0] MASK, WDATA
553 parameter WRITE_MODE = 0;
554 parameter READ_MODE = 0;
556 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
557 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
558 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
559 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
560 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
561 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
562 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
563 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
564 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
565 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
566 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
567 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
568 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
569 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
570 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
571 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
573 parameter INIT_FILE = "";
576 .WRITE_MODE(WRITE_MODE),
577 .READ_MODE (READ_MODE ),
594 .INIT_FILE (INIT_FILE )
610 module SB_RAM40_4KNRNW (
612 input RCLKN, RCLKE, RE,
614 input WCLKN, WCLKE, WE,
616 input [15:0] MASK, WDATA
618 parameter WRITE_MODE = 0;
619 parameter READ_MODE = 0;
621 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
622 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
623 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
624 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
625 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
626 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
627 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
628 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
629 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
630 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
631 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
632 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
633 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
634 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
635 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
636 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
638 parameter INIT_FILE = "";
641 .WRITE_MODE(WRITE_MODE),
642 .READ_MODE (READ_MODE ),
659 .INIT_FILE (INIT_FILE )
675 // Packed IceStorm Logic Cells
678 input I0, I1, I2, I3, CIN, CLK, CEN, SR,
681 parameter [15:0] LUT_INIT = 0;
683 parameter [0:0] NEG_CLK = 0;
684 parameter [0:0] CARRY_ENABLE = 0;
685 parameter [0:0] DFF_ENABLE = 0;
686 parameter [0:0] SET_NORESET = 0;
687 parameter [0:0] ASYNC_SR = 0;
689 parameter [0:0] CIN_CONST = 0;
690 parameter [0:0] CIN_SET = 0;
692 wire mux_cin = CIN_CONST ? CIN_SET : CIN;
694 assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && mux_cin) : 1'bx;
696 wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
697 wire [3:0] lut_s2 = I2 ? lut_s3[ 7:4] : lut_s3[3:0];
698 wire [1:0] lut_s1 = I1 ? lut_s2[ 3:2] : lut_s2[1:0];
699 wire lut_o = I0 ? lut_s1[ 1] : lut_s1[ 0];
704 assign polarized_clk = CLK ^ NEG_CLK;
707 always @(posedge polarized_clk)
709 o_reg <= SR ? SET_NORESET : lut_o;
712 always @(posedge polarized_clk, posedge SR)
714 o_reg <= SET_NORESET;
718 assign O = DFF_ENABLE ? ASYNC_SR ? o_reg_async : o_reg : lut_o;
721 // SiliconBlue PLL Cells
724 module SB_PLL40_CORE (
729 input [7:0] DYNAMICDELAY,
733 input LATCHINPUTVALUE,
738 parameter FEEDBACK_PATH = "SIMPLE";
739 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
740 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
741 parameter SHIFTREG_DIV_MODE = 1'b0;
742 parameter FDA_FEEDBACK = 4'b0000;
743 parameter FDA_RELATIVE = 4'b0000;
744 parameter PLLOUT_SELECT = "GENCLK";
745 parameter DIVR = 4'b0000;
746 parameter DIVF = 7'b0000000;
747 parameter DIVQ = 3'b000;
748 parameter FILTER_RANGE = 3'b000;
749 parameter ENABLE_ICEGATE = 1'b0;
750 parameter TEST_MODE = 1'b0;
751 parameter EXTERNAL_DIVIDE_FACTOR = 1;
755 module SB_PLL40_PAD (
760 input [7:0] DYNAMICDELAY,
764 input LATCHINPUTVALUE,
769 parameter FEEDBACK_PATH = "SIMPLE";
770 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
771 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
772 parameter SHIFTREG_DIV_MODE = 1'b0;
773 parameter FDA_FEEDBACK = 4'b0000;
774 parameter FDA_RELATIVE = 4'b0000;
775 parameter PLLOUT_SELECT = "GENCLK";
776 parameter DIVR = 4'b0000;
777 parameter DIVF = 7'b0000000;
778 parameter DIVQ = 3'b000;
779 parameter FILTER_RANGE = 3'b000;
780 parameter ENABLE_ICEGATE = 1'b0;
781 parameter TEST_MODE = 1'b0;
782 parameter EXTERNAL_DIVIDE_FACTOR = 1;
786 module SB_PLL40_2_PAD (
789 output PLLOUTGLOBALA,
791 output PLLOUTGLOBALB,
793 input [7:0] DYNAMICDELAY,
797 input LATCHINPUTVALUE,
802 parameter FEEDBACK_PATH = "SIMPLE";
803 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
804 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
805 parameter SHIFTREG_DIV_MODE = 1'b0;
806 parameter FDA_FEEDBACK = 4'b0000;
807 parameter FDA_RELATIVE = 4'b0000;
808 parameter PLLOUT_SELECT_PORTB = "GENCLK";
809 parameter DIVR = 4'b0000;
810 parameter DIVF = 7'b0000000;
811 parameter DIVQ = 3'b000;
812 parameter FILTER_RANGE = 3'b000;
813 parameter ENABLE_ICEGATE_PORTA = 1'b0;
814 parameter ENABLE_ICEGATE_PORTB = 1'b0;
815 parameter TEST_MODE = 1'b0;
816 parameter EXTERNAL_DIVIDE_FACTOR = 1;
820 module SB_PLL40_2F_CORE (
823 output PLLOUTGLOBALA,
825 output PLLOUTGLOBALB,
827 input [7:0] DYNAMICDELAY,
831 input LATCHINPUTVALUE,
836 parameter FEEDBACK_PATH = "SIMPLE";
837 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
838 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
839 parameter SHIFTREG_DIV_MODE = 1'b0;
840 parameter FDA_FEEDBACK = 4'b0000;
841 parameter FDA_RELATIVE = 4'b0000;
842 parameter PLLOUT_SELECT_PORTA = "GENCLK";
843 parameter PLLOUT_SELECT_PORTB = "GENCLK";
844 parameter DIVR = 4'b0000;
845 parameter DIVF = 7'b0000000;
846 parameter DIVQ = 3'b000;
847 parameter FILTER_RANGE = 3'b000;
848 parameter ENABLE_ICEGATE_PORTA = 1'b0;
849 parameter ENABLE_ICEGATE_PORTB = 1'b0;
850 parameter TEST_MODE = 1'b0;
851 parameter EXTERNAL_DIVIDE_FACTOR = 1;
855 module SB_PLL40_2F_PAD (
858 output PLLOUTGLOBALA,
860 output PLLOUTGLOBALB,
862 input [7:0] DYNAMICDELAY,
866 input LATCHINPUTVALUE,
871 parameter FEEDBACK_PATH = "SIMPLE";
872 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
873 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
874 parameter SHIFTREG_DIV_MODE = 2'b00;
875 parameter FDA_FEEDBACK = 4'b0000;
876 parameter FDA_RELATIVE = 4'b0000;
877 parameter PLLOUT_SELECT_PORTA = "GENCLK";
878 parameter PLLOUT_SELECT_PORTB = "GENCLK";
879 parameter DIVR = 4'b0000;
880 parameter DIVF = 7'b0000000;
881 parameter DIVQ = 3'b000;
882 parameter FILTER_RANGE = 3'b000;
883 parameter ENABLE_ICEGATE_PORTA = 1'b0;
884 parameter ENABLE_ICEGATE_PORTB = 1'b0;
885 parameter TEST_MODE = 1'b0;
886 parameter EXTERNAL_DIVIDE_FACTOR = 1;
889 // SiliconBlue Device Configuration Cells
900 module SB_SPRAM256KA (
901 input [13:0] ADDRESS,
903 input [3:0] MASKWREN,
904 input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
905 output reg [15:0] DATAOUT
909 reg [15:0] mem [0:16383];
910 wire off = SLEEP || !POWEROFF;
913 always @(negedge POWEROFF) begin
914 for (i = 0; i <= 16383; i = i+1)
918 always @(posedge CLOCK, posedge off) begin
922 if (CHIPSELECT && !STANDBY && !WREN) begin
923 DATAOUT <= mem[ADDRESS];
925 if (CHIPSELECT && !STANDBY && WREN) begin
926 if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0];
927 if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4];
928 if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8];
929 if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12];
954 parameter TRIM_EN = "0b0";
955 parameter CLKHF_DIV = "0b00";
977 parameter CURRENT_MODE = "0b0";
978 parameter RGB0_CURRENT = "0b000000";
979 parameter RGB1_CURRENT = "0b000000";
980 parameter RGB2_CURRENT = "0b000000";
984 module SB_LED_DRV_CUR(
1001 parameter CURRENT_MODE = "0b0";
1002 parameter RGB0_CURRENT = "0b000000";
1003 parameter RGB1_CURRENT = "0b000000";
1004 parameter RGB2_CURRENT = "0b000000";
1041 output SCLO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
1046 parameter I2C_SLAVE_INIT_ADDR = "0b1111100001";
1047 parameter BUS_ADDR74 = "0b0001";
1090 output SCKO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
1101 parameter BUS_ADDR74 = "0b0000";
1131 module SB_FILTER_50NS(
1139 input LATCH_INPUT_VALUE,
1143 input OUTPUT_ENABLE,
1151 parameter [5:0] PIN_TYPE = 6'b000000;
1152 parameter [0:0] PULLUP = 1'b0;
1153 parameter [0:0] WEAK_PULLUP = 1'b0;
1154 parameter [0:0] NEG_TRIGGER = 1'b0;
1155 parameter IO_STANDARD = "SB_LVCMOS";
1158 reg dout, din_0, din_1;
1159 reg din_q_0, din_q_1;
1160 reg dout_q_0, dout_q_1;
1163 generate if (!NEG_TRIGGER) begin
1164 always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
1165 always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
1166 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
1167 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
1168 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
1170 always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
1171 always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
1172 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
1173 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
1174 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
1178 if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
1179 din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
1183 // work around simulation glitches on dout in DDR mode
1184 reg outclk_delayed_1;
1185 reg outclk_delayed_2;
1186 always @* outclk_delayed_1 <= OUTPUT_CLK;
1187 always @* outclk_delayed_2 <= outclk_delayed_1;
1191 dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
1193 dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
1196 assign D_IN_0 = din_0, D_IN_1 = din_1;
1199 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
1200 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
1201 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
1208 input LATCHINPUTVALUE,
1218 parameter [5:0] PIN_TYPE = 6'b000000;
1219 parameter [0:0] NEG_TRIGGER = 1'b0;
1222 reg dout, din_0, din_1;
1223 reg din_q_0, din_q_1;
1224 reg dout_q_0, dout_q_1;
1227 generate if (!NEG_TRIGGER) begin
1228 always @(posedge INPUTCLK) if (CLOCKENABLE) din_q_0 <= PACKAGEPIN;
1229 always @(negedge INPUTCLK) if (CLOCKENABLE) din_q_1 <= PACKAGEPIN;
1230 always @(posedge OUTPUTCLK) if (CLOCKENABLE) dout_q_0 <= DOUT0;
1231 always @(negedge OUTPUTCLK) if (CLOCKENABLE) dout_q_1 <= DOUT1;
1232 always @(posedge OUTPUTCLK) if (CLOCKENABLE) outena_q <= OUTPUTENABLE;
1234 always @(negedge INPUTCLK) if (CLOCKENABLE) din_q_0 <= PACKAGEPIN;
1235 always @(posedge INPUTCLK) if (CLOCKENABLE) din_q_1 <= PACKAGEPIN;
1236 always @(negedge OUTPUTCLK) if (CLOCKENABLE) dout_q_0 <= DOUT0;
1237 always @(posedge OUTPUTCLK) if (CLOCKENABLE) dout_q_1 <= DOUT1;
1238 always @(negedge OUTPUTCLK) if (CLOCKENABLE) outena_q <= OUTPUTENABLE;
1242 if (!PIN_TYPE[1] || !LATCHINPUTVALUE)
1243 din_0 = PIN_TYPE[0] ? PACKAGEPIN : din_q_0;
1247 // work around simulation glitches on dout in DDR mode
1248 reg outclk_delayed_1;
1249 reg outclk_delayed_2;
1250 always @* outclk_delayed_1 <= OUTPUTCLK;
1251 always @* outclk_delayed_2 <= outclk_delayed_1;
1255 dout = PIN_TYPE[2] ? !dout_q_0 : DOUT0;
1257 dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
1260 assign DIN0 = din_0, DIN1 = din_1;
1263 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGEPIN = dout ? 1'bz : 1'b0;
1264 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGEPIN = OUTPUTENABLE ? (dout ? 1'bz : 1'b0) : 1'bz;
1265 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGEPIN = outena_q ? (dout ? 1'bz : 1'b0) : 1'bz;
1272 input [15:0] C, A, B, D,
1273 input AHOLD, BHOLD, CHOLD, DHOLD,
1274 input IRSTTOP, IRSTBOT,
1275 input ORSTTOP, ORSTBOT,
1276 input OLOADTOP, OLOADBOT,
1277 input ADDSUBTOP, ADDSUBBOT,
1278 input OHOLDTOP, OHOLDBOT,
1279 input CI, ACCUMCI, SIGNEXTIN,
1281 output CO, ACCUMCO, SIGNEXTOUT
1283 parameter [0:0] NEG_TRIGGER = 0;
1284 parameter [0:0] C_REG = 0;
1285 parameter [0:0] A_REG = 0;
1286 parameter [0:0] B_REG = 0;
1287 parameter [0:0] D_REG = 0;
1288 parameter [0:0] TOP_8x8_MULT_REG = 0;
1289 parameter [0:0] BOT_8x8_MULT_REG = 0;
1290 parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
1291 parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
1292 parameter [1:0] TOPOUTPUT_SELECT = 0;
1293 parameter [1:0] TOPADDSUB_LOWERINPUT = 0;
1294 parameter [0:0] TOPADDSUB_UPPERINPUT = 0;
1295 parameter [1:0] TOPADDSUB_CARRYSELECT = 0;
1296 parameter [1:0] BOTOUTPUT_SELECT = 0;
1297 parameter [1:0] BOTADDSUB_LOWERINPUT = 0;
1298 parameter [0:0] BOTADDSUB_UPPERINPUT = 0;
1299 parameter [1:0] BOTADDSUB_CARRYSELECT = 0;
1300 parameter [0:0] MODE_8x8 = 0;
1301 parameter [0:0] A_SIGNED = 0;
1302 parameter [0:0] B_SIGNED = 0;
1304 wire clock = CLK ^ NEG_TRIGGER;
1306 // internal wires, compare Figure on page 133 of ICE Technology Library 3.0 and Fig 2 on page 2 of Lattice TN1295-DSP
1307 // http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201608.pdf
1308 // https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/AD/DSPFunctionUsageGuideforICE40Devices.ashx
1309 wire [15:0] iA, iB, iC, iD;
1310 wire [15:0] iF, iJ, iK, iG;
1312 wire [15:0] iW, iX, iP, iQ;
1313 wire [15:0] iY, iZ, iR, iS;
1318 always @(posedge clock, posedge IRSTTOP) begin
1322 end else if (CE) begin
1323 if (!CHOLD) rC <= C;
1324 if (!AHOLD) rA <= A;
1327 assign iC = C_REG ? rC : C;
1328 assign iA = A_REG ? rA : A;
1332 always @(posedge clock, posedge IRSTBOT) begin
1336 end else if (CE) begin
1337 if (!BHOLD) rB <= B;
1338 if (!DHOLD) rD <= D;
1341 assign iB = B_REG ? rB : B;
1342 assign iD = D_REG ? rD : D;
1345 wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
1346 wire [15:0] Ah, Al, Bh, Bl;
1347 assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]};
1348 assign Al = {A_SIGNED ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
1349 assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]};
1350 assign Bl = {B_SIGNED ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
1351 assign p_Ah_Bh = Ah * Bh;
1352 assign p_Al_Bh = Al * Bh;
1353 assign p_Ah_Bl = Ah * Bl;
1354 assign p_Al_Bl = Al * Bl;
1358 always @(posedge clock, posedge IRSTTOP) begin
1362 end else if (CE) begin
1364 if (!MODE_8x8) rJ <= p_Al_Bh;
1367 assign iF = TOP_8x8_MULT_REG ? rF : p_Ah_Bh;
1368 assign iJ = PIPELINE_16x16_MULT_REG1 ? rJ : p_Al_Bh;
1372 always @(posedge clock, posedge IRSTBOT) begin
1376 end else if (CE) begin
1377 if (!MODE_8x8) rK <= p_Ah_Bl;
1381 assign iK = PIPELINE_16x16_MULT_REG1 ? rK : p_Ah_Bl;
1382 assign iG = BOT_8x8_MULT_REG ? rG : p_Al_Bl;
1385 assign iL = iG + (iK << 8) + (iJ << 8) + (iF << 16);
1389 always @(posedge clock, posedge IRSTBOT) begin
1392 end else if (CE) begin
1393 if (!MODE_8x8) rH <= iL;
1396 assign iH = PIPELINE_16x16_MULT_REG2 ? rH : iL;
1401 assign iW = TOPADDSUB_UPPERINPUT ? iC : iQ;
1402 assign iX = (TOPADDSUB_LOWERINPUT == 0) ? iA : (TOPADDSUB_LOWERINPUT == 1) ? iF : (TOPADDSUB_LOWERINPUT == 2) ? iH[31:16] : {16{iZ[15]}};
1403 assign {ACCUMCO, XW} = iX + (iW ^ {16{ADDSUBTOP}}) + HCI;
1404 assign CO = ACCUMCO ^ ADDSUBTOP;
1405 assign iP = OLOADTOP ? iC : XW ^ {16{ADDSUBTOP}};
1406 always @(posedge clock, posedge ORSTTOP) begin
1409 end else if (CE) begin
1410 if (!OHOLDTOP) rQ <= iP;
1414 assign Oh = (TOPOUTPUT_SELECT == 0) ? iP : (TOPOUTPUT_SELECT == 1) ? iQ : (TOPOUTPUT_SELECT == 2) ? iF : iH[31:16];
1415 assign HCI = (TOPADDSUB_CARRYSELECT == 0) ? 1'b0 : (TOPADDSUB_CARRYSELECT == 1) ? 1'b1 : (TOPADDSUB_CARRYSELECT == 2) ? LCO : LCO ^ ADDSUBBOT;
1416 assign SIGNEXTOUT = iX[15];
1421 assign iY = BOTADDSUB_UPPERINPUT ? iD : iS;
1422 assign iZ = (BOTADDSUB_LOWERINPUT == 0) ? iB : (BOTADDSUB_LOWERINPUT == 1) ? iG : (BOTADDSUB_LOWERINPUT == 2) ? iH[15:0] : {16{SIGNEXTIN}};
1423 assign {LCO, YZ} = iZ + (iY ^ {16{ADDSUBBOT}}) + LCI;
1424 assign iR = OLOADBOT ? iD : YZ ^ {16{ADDSUBBOT}};
1425 always @(posedge clock, posedge ORSTBOT) begin
1428 end else if (CE) begin
1429 if (!OHOLDBOT) rS <= iR;
1433 assign Ol = (BOTOUTPUT_SELECT == 0) ? iR : (BOTOUTPUT_SELECT == 1) ? iS : (BOTOUTPUT_SELECT == 2) ? iG : iH[15:0];
1434 assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI;
1435 assign O = {Oh, Ol};