projects / yosys.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
[yosys.git] / techlibs / ice40 / cells_sim.v
1
2 `define SB_DFF_REG reg Q = 0
3 // `define SB_DFF_REG reg Q
4
5 // SiliconBlue IO Cells
6
7 module SB_IO (
8 inout PACKAGE_PIN,
9 input LATCH_INPUT_VALUE,
10 input CLOCK_ENABLE,
11 input INPUT_CLK,
12 input OUTPUT_CLK,
13 input OUTPUT_ENABLE,
14 input D_OUT_0,
15 input D_OUT_1,
16 output D_IN_0,
17 output D_IN_1
18 );
19 parameter [5:0] PIN_TYPE = 6'b000000;
20 parameter [0:0] PULLUP = 1'b0;
21 parameter [0:0] NEG_TRIGGER = 1'b0;
22 parameter IO_STANDARD = "SB_LVCMOS";
23
24 `ifndef BLACKBOX
25 reg dout, din_0, din_1;
26 reg din_q_0, din_q_1;
27 reg dout_q_0, dout_q_1;
28 reg outena_q;
29
30 // IO tile generates a constant 1'b1 internally if global_cen is not connected
31 wire clken_pulled = CLOCK_ENABLE || CLOCK_ENABLE === 1'bz;
32 reg clken_pulled_ri;
33 reg clken_pulled_ro;
34
35 generate if (!NEG_TRIGGER) begin
36 always @(posedge INPUT_CLK) clken_pulled_ri <= clken_pulled;
37 always @(posedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN;
38 always @(negedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN;
39 always @(posedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled;
40 always @(posedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0;
41 always @(negedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1;
42 always @(posedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE;
43 end else begin
44 always @(negedge INPUT_CLK) clken_pulled_ri <= clken_pulled;
45 always @(negedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN;
46 always @(posedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN;
47 always @(negedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled;
48 always @(negedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0;
49 always @(posedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1;
50 always @(negedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE;
51 end endgenerate
52
53 always @* begin
54 if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
55 din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
56 din_1 = din_q_1;
57 end
58
59 // work around simulation glitches on dout in DDR mode
60 reg outclk_delayed_1;
61 reg outclk_delayed_2;
62 always @* outclk_delayed_1 <= OUTPUT_CLK;
63 always @* outclk_delayed_2 <= outclk_delayed_1;
64
65 always @* begin
66 if (PIN_TYPE[3])
67 dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
68 else
69 dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
70 end
71
72 assign D_IN_0 = din_0, D_IN_1 = din_1;
73
74 generate
75 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
76 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
77 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
78 endgenerate
79 `endif
80 endmodule
81
82 module SB_GB_IO (
83 inout PACKAGE_PIN,
84 output GLOBAL_BUFFER_OUTPUT,
85 input LATCH_INPUT_VALUE,
86 input CLOCK_ENABLE,
87 input INPUT_CLK,
88 input OUTPUT_CLK,
89 input OUTPUT_ENABLE,
90 input D_OUT_0,
91 input D_OUT_1,
92 output D_IN_0,
93 output D_IN_1
94 );
95 parameter [5:0] PIN_TYPE = 6'b000000;
96 parameter [0:0] PULLUP = 1'b0;
97 parameter [0:0] NEG_TRIGGER = 1'b0;
98 parameter IO_STANDARD = "SB_LVCMOS";
99
100 assign GLOBAL_BUFFER_OUTPUT = PACKAGE_PIN;
101
102 SB_IO #(
103 .PIN_TYPE(PIN_TYPE),
104 .PULLUP(PULLUP),
105 .NEG_TRIGGER(NEG_TRIGGER),
106 .IO_STANDARD(IO_STANDARD)
107 ) IO (
108 .PACKAGE_PIN(PACKAGE_PIN),
109 .LATCH_INPUT_VALUE(LATCH_INPUT_VALUE),
110 .CLOCK_ENABLE(CLOCK_ENABLE),
111 .INPUT_CLK(INPUT_CLK),
112 .OUTPUT_CLK(OUTPUT_CLK),
113 .OUTPUT_ENABLE(OUTPUT_ENABLE),
114 .D_OUT_0(D_OUT_0),
115 .D_OUT_1(D_OUT_1),
116 .D_IN_0(D_IN_0),
117 .D_IN_1(D_IN_1)
118 );
119 endmodule
120
121 module SB_GB (
122 input USER_SIGNAL_TO_GLOBAL_BUFFER,
123 output GLOBAL_BUFFER_OUTPUT
124 );
125 assign GLOBAL_BUFFER_OUTPUT = USER_SIGNAL_TO_GLOBAL_BUFFER;
126 endmodule
127
128 // SiliconBlue Logic Cells
129
130 (* abc_box_id = 22, lib_whitebox *)
131 module SB_LUT4 (output O, input I0, I1, I2, I3);
132 parameter [15:0] LUT_INIT = 0;
133 wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
134 wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
135 wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];
136 assign O = I0 ? s1[1] : s1[0];
137 endmodule
138
139 (* abc_box_id = 21, abc_carry, lib_whitebox *)
140 module SB_CARRY ((* abc_carry_out *) output CO, input I0, I1, (* abc_carry_in *) input CI);
141 assign CO = (I0 && I1) || ((I0 || I1) && CI);
142 endmodule
143
144 // Positive Edge SiliconBlue FF Cells
145
146 (* abc_box_id = 1, abc_flop, lib_whitebox *)
147 module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
148 `ifndef _ABC
149 always @(posedge C)
150 Q <= D;
151 `else
152 always @* Q <= D;
153 `endif
154 endmodule
155
156 //(* abc_box_id = 2, abc_flop *)
157 module SB_DFFE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, (* abc_flop_d *) input D);
158 always @(posedge C)
159 if (E)
160 Q <= D;
161 endmodule
162
163 //(* abc_box_id = 3, abc_flop *)
164 module SB_DFFSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
165 always @(posedge C)
166 if (R)
167 Q <= 0;
168 else
169 Q <= D;
170 endmodule
171
172 //(* abc_box_id = 4, abc_flop *)
173 module SB_DFFR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
174 always @(posedge C, posedge R)
175 if (R)
176 Q <= 0;
177 else
178 Q <= D;
179 endmodule
180
181 //(* abc_box_id = 5, abc_flop *)
182 module SB_DFFSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
183 always @(posedge C)
184 if (S)
185 Q <= 1;
186 else
187 Q <= D;
188 endmodule
189
190 //(* abc_box_id = 6, abc_flop *)
191 module SB_DFFS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
192 always @(posedge C, posedge S)
193 if (S)
194 Q <= 1;
195 else
196 Q <= D;
197 endmodule
198
199 //(* abc_box_id = 7, abc_flop *)
200 module SB_DFFESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
201 always @(posedge C)
202 if (E) begin
203 if (R)
204 Q <= 0;
205 else
206 Q <= D;
207 end
208 endmodule
209
210 //(* abc_box_id = 8, abc_flop *)
211 module SB_DFFER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
212 always @(posedge C, posedge R)
213 if (R)
214 Q <= 0;
215 else if (E)
216 Q <= D;
217 endmodule
218
219 //(* abc_box_id = 9, abc_flop *)
220 module SB_DFFESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
221 always @(posedge C)
222 if (E) begin
223 if (S)
224 Q <= 1;
225 else
226 Q <= D;
227 end
228 endmodule
229
230 //(* abc_box_id = 10, abc_flop *)
231 module SB_DFFES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
232 always @(posedge C, posedge S)
233 if (S)
234 Q <= 1;
235 else if (E)
236 Q <= D;
237 endmodule
238
239 // Negative Edge SiliconBlue FF Cells
240
241 //(* abc_box_id = 11, abc_flop *)
242 module SB_DFFN ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
243 always @(negedge C)
244 Q <= D;
245 endmodule
246
247 //(* abc_box_id = 12, abc_flop *)
248 module SB_DFFNE ((* abc_flop_q *) output `SB_DFF_REG, input C, E, (* abc_flop_d *) input D);
249 always @(negedge C)
250 if (E)
251 Q <= D;
252 endmodule
253
254 //(* abc_box_id = 13, abc_flop *)
255 module SB_DFFNSR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
256 always @(negedge C)
257 if (R)
258 Q <= 0;
259 else
260 Q <= D;
261 endmodule
262
263 //(* abc_box_id = 14, abc_flop *)
264 module SB_DFFNR ((* abc_flop_q *) output `SB_DFF_REG, input C, R, (* abc_flop_d *) input D);
265 always @(negedge C, posedge R)
266 if (R)
267 Q <= 0;
268 else
269 Q <= D;
270 endmodule
271
272 //(* abc_box_id = 15, abc_flop *)
273 module SB_DFFNSS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
274 always @(negedge C)
275 if (S)
276 Q <= 1;
277 else
278 Q <= D;
279 endmodule
280
281 //(* abc_box_id = 16, abc_flop *)
282 module SB_DFFNS ((* abc_flop_q *) output `SB_DFF_REG, input C, S, (* abc_flop_d *) input D);
283 always @(negedge C, posedge S)
284 if (S)
285 Q <= 1;
286 else
287 Q <= D;
288 endmodule
289
290 //(* abc_box_id = 17, abc_flop *)
291 module SB_DFFNESR ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
292 always @(negedge C)
293 if (E) begin
294 if (R)
295 Q <= 0;
296 else
297 Q <= D;
298 end
299 endmodule
300
301 //(* abc_box_id = 18, abc_flop *)
302 module SB_DFFNER ((* abc_flop_q *) output `SB_DFF_REG, input C, E, R, (* abc_flop_d *) input D);
303 always @(negedge C, posedge R)
304 if (R)
305 Q <= 0;
306 else if (E)
307 Q <= D;
308 endmodule
309
310 //(* abc_box_id = 19, abc_flop *)
311 module SB_DFFNESS ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
312 always @(negedge C)
313 if (E) begin
314 if (S)
315 Q <= 1;
316 else
317 Q <= D;
318 end
319 endmodule
320
321 //(* abc_box_id = 20, abc_flop *)
322 module SB_DFFNES ((* abc_flop_q *) output `SB_DFF_REG, input C, E, S, (* abc_flop_d *) input D);
323 always @(negedge C, posedge S)
324 if (S)
325 Q <= 1;
326 else if (E)
327 Q <= D;
328 endmodule
329
330 // SiliconBlue RAM Cells
331
332 module SB_RAM40_4K (
333 (* abc_flop_q *) output [15:0] RDATA,
334 input RCLK, RCLKE, RE,
335 input [10:0] RADDR,
336 input WCLK, WCLKE, WE,
337 input [10:0] WADDR,
338 input [15:0] MASK, WDATA
339 );
340 // MODE 0: 256 x 16
341 // MODE 1: 512 x 8
342 // MODE 2: 1024 x 4
343 // MODE 3: 2048 x 2
344 parameter WRITE_MODE = 0;
345 parameter READ_MODE = 0;
346
347 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
348 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
349 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
350 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
351 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
352 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
353 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
354 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
355 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
356 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
357 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
358 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
359 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
360 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
361 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
362 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
363
364 parameter INIT_FILE = "";
365
366 `ifndef BLACKBOX
367 wire [15:0] WMASK_I;
368 wire [15:0] RMASK_I;
369
370 reg [15:0] RDATA_I;
371 wire [15:0] WDATA_I;
372
373 generate
374 case (WRITE_MODE)
375 0: assign WMASK_I = MASK;
376
377 1: assign WMASK_I = WADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
378 WADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
379
380 2: assign WMASK_I = WADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
381 WADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
382 WADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
383 WADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
384
385 3: assign WMASK_I = WADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
386 WADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
387 WADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
388 WADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
389 WADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
390 WADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
391 WADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
392 WADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
393 endcase
394
395 case (READ_MODE)
396 0: assign RMASK_I = 16'b 0000_0000_0000_0000;
397
398 1: assign RMASK_I = RADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
399 RADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
400
401 2: assign RMASK_I = RADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
402 RADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
403 RADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
404 RADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
405
406 3: assign RMASK_I = RADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
407 RADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
408 RADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
409 RADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
410 RADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
411 RADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
412 RADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
413 RADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
414 endcase
415
416 case (WRITE_MODE)
417 0: assign WDATA_I = WDATA;
418
419 1: assign WDATA_I = {WDATA[14], WDATA[14], WDATA[12], WDATA[12],
420 WDATA[10], WDATA[10], WDATA[ 8], WDATA[ 8],
421 WDATA[ 6], WDATA[ 6], WDATA[ 4], WDATA[ 4],
422 WDATA[ 2], WDATA[ 2], WDATA[ 0], WDATA[ 0]};
423
424 2: assign WDATA_I = {WDATA[13], WDATA[13], WDATA[13], WDATA[13],
425 WDATA[ 9], WDATA[ 9], WDATA[ 9], WDATA[ 9],
426 WDATA[ 5], WDATA[ 5], WDATA[ 5], WDATA[ 5],
427 WDATA[ 1], WDATA[ 1], WDATA[ 1], WDATA[ 1]};
428
429 3: assign WDATA_I = {WDATA[11], WDATA[11], WDATA[11], WDATA[11],
430 WDATA[11], WDATA[11], WDATA[11], WDATA[11],
431 WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3],
432 WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3]};
433 endcase
434
435 case (READ_MODE)
436 0: assign RDATA = RDATA_I;
437 1: assign RDATA = {1'b0, |RDATA_I[15:14], 1'b0, |RDATA_I[13:12], 1'b0, |RDATA_I[11:10], 1'b0, |RDATA_I[ 9: 8],
438 1'b0, |RDATA_I[ 7: 6], 1'b0, |RDATA_I[ 5: 4], 1'b0, |RDATA_I[ 3: 2], 1'b0, |RDATA_I[ 1: 0]};
439 2: assign RDATA = {2'b0, |RDATA_I[15:12], 3'b0, |RDATA_I[11: 8], 3'b0, |RDATA_I[ 7: 4], 3'b0, |RDATA_I[ 3: 0], 1'b0};
440 3: assign RDATA = {4'b0, |RDATA_I[15: 8], 7'b0, |RDATA_I[ 7: 0], 3'b0};
441 endcase
442 endgenerate
443
444 integer i;
445 reg [15:0] memory [0:255];
446
447 initial begin
448 if (INIT_FILE != "")
449 $readmemh(INIT_FILE, memory);
450 else
451 for (i=0; i<16; i=i+1) begin
452 memory[ 0*16 + i] = INIT_0[16*i +: 16];
453 memory[ 1*16 + i] = INIT_1[16*i +: 16];
454 memory[ 2*16 + i] = INIT_2[16*i +: 16];
455 memory[ 3*16 + i] = INIT_3[16*i +: 16];
456 memory[ 4*16 + i] = INIT_4[16*i +: 16];
457 memory[ 5*16 + i] = INIT_5[16*i +: 16];
458 memory[ 6*16 + i] = INIT_6[16*i +: 16];
459 memory[ 7*16 + i] = INIT_7[16*i +: 16];
460 memory[ 8*16 + i] = INIT_8[16*i +: 16];
461 memory[ 9*16 + i] = INIT_9[16*i +: 16];
462 memory[10*16 + i] = INIT_A[16*i +: 16];
463 memory[11*16 + i] = INIT_B[16*i +: 16];
464 memory[12*16 + i] = INIT_C[16*i +: 16];
465 memory[13*16 + i] = INIT_D[16*i +: 16];
466 memory[14*16 + i] = INIT_E[16*i +: 16];
467 memory[15*16 + i] = INIT_F[16*i +: 16];
468 end
469 end
470
471 always @(posedge WCLK) begin
472 if (WE && WCLKE) begin
473 if (!WMASK_I[ 0]) memory[WADDR[7:0]][ 0] <= WDATA_I[ 0];
474 if (!WMASK_I[ 1]) memory[WADDR[7:0]][ 1] <= WDATA_I[ 1];
475 if (!WMASK_I[ 2]) memory[WADDR[7:0]][ 2] <= WDATA_I[ 2];
476 if (!WMASK_I[ 3]) memory[WADDR[7:0]][ 3] <= WDATA_I[ 3];
477 if (!WMASK_I[ 4]) memory[WADDR[7:0]][ 4] <= WDATA_I[ 4];
478 if (!WMASK_I[ 5]) memory[WADDR[7:0]][ 5] <= WDATA_I[ 5];
479 if (!WMASK_I[ 6]) memory[WADDR[7:0]][ 6] <= WDATA_I[ 6];
480 if (!WMASK_I[ 7]) memory[WADDR[7:0]][ 7] <= WDATA_I[ 7];
481 if (!WMASK_I[ 8]) memory[WADDR[7:0]][ 8] <= WDATA_I[ 8];
482 if (!WMASK_I[ 9]) memory[WADDR[7:0]][ 9] <= WDATA_I[ 9];
483 if (!WMASK_I[10]) memory[WADDR[7:0]][10] <= WDATA_I[10];
484 if (!WMASK_I[11]) memory[WADDR[7:0]][11] <= WDATA_I[11];
485 if (!WMASK_I[12]) memory[WADDR[7:0]][12] <= WDATA_I[12];
486 if (!WMASK_I[13]) memory[WADDR[7:0]][13] <= WDATA_I[13];
487 if (!WMASK_I[14]) memory[WADDR[7:0]][14] <= WDATA_I[14];
488 if (!WMASK_I[15]) memory[WADDR[7:0]][15] <= WDATA_I[15];
489 end
490 end
491
492 always @(posedge RCLK) begin
493 if (RE && RCLKE) begin
494 RDATA_I <= memory[RADDR[7:0]] & ~RMASK_I;
495 end
496 end
497 `endif
498 endmodule
499
500 module SB_RAM40_4KNR (
501 (* abc_flop_q *) output [15:0] RDATA,
502 input RCLKN, RCLKE, RE,
503 input [10:0] RADDR,
504 input WCLK, WCLKE, WE,
505 input [10:0] WADDR,
506 input [15:0] MASK, WDATA
507 );
508 parameter WRITE_MODE = 0;
509 parameter READ_MODE = 0;
510
511 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
512 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
513 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
514 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
515 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
516 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
517 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
518 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
519 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
520 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
521 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
522 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
523 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
524 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
525 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
526 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
527
528 parameter INIT_FILE = "";
529
530 SB_RAM40_4K #(
531 .WRITE_MODE(WRITE_MODE),
532 .READ_MODE (READ_MODE ),
533 .INIT_0 (INIT_0 ),
534 .INIT_1 (INIT_1 ),
535 .INIT_2 (INIT_2 ),
536 .INIT_3 (INIT_3 ),
537 .INIT_4 (INIT_4 ),
538 .INIT_5 (INIT_5 ),
539 .INIT_6 (INIT_6 ),
540 .INIT_7 (INIT_7 ),
541 .INIT_8 (INIT_8 ),
542 .INIT_9 (INIT_9 ),
543 .INIT_A (INIT_A ),
544 .INIT_B (INIT_B ),
545 .INIT_C (INIT_C ),
546 .INIT_D (INIT_D ),
547 .INIT_E (INIT_E ),
548 .INIT_F (INIT_F ),
549 .INIT_FILE (INIT_FILE )
550 ) RAM (
551 .RDATA(RDATA),
552 .RCLK (~RCLKN),
553 .RCLKE(RCLKE),
554 .RE (RE ),
555 .RADDR(RADDR),
556 .WCLK (WCLK ),
557 .WCLKE(WCLKE),
558 .WE (WE ),
559 .WADDR(WADDR),
560 .MASK (MASK ),
561 .WDATA(WDATA)
562 );
563 endmodule
564
565 module SB_RAM40_4KNW (
566 (* abc_flop_q *) output [15:0] RDATA,
567 input RCLK, RCLKE, RE,
568 input [10:0] RADDR,
569 input WCLKN, WCLKE, WE,
570 input [10:0] WADDR,
571 input [15:0] MASK, WDATA
572 );
573 parameter WRITE_MODE = 0;
574 parameter READ_MODE = 0;
575
576 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
577 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
578 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
579 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
580 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
581 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
582 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
583 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
584 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
585 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
586 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
587 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
588 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
589 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
590 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
591 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
592
593 parameter INIT_FILE = "";
594
595 SB_RAM40_4K #(
596 .WRITE_MODE(WRITE_MODE),
597 .READ_MODE (READ_MODE ),
598 .INIT_0 (INIT_0 ),
599 .INIT_1 (INIT_1 ),
600 .INIT_2 (INIT_2 ),
601 .INIT_3 (INIT_3 ),
602 .INIT_4 (INIT_4 ),
603 .INIT_5 (INIT_5 ),
604 .INIT_6 (INIT_6 ),
605 .INIT_7 (INIT_7 ),
606 .INIT_8 (INIT_8 ),
607 .INIT_9 (INIT_9 ),
608 .INIT_A (INIT_A ),
609 .INIT_B (INIT_B ),
610 .INIT_C (INIT_C ),
611 .INIT_D (INIT_D ),
612 .INIT_E (INIT_E ),
613 .INIT_F (INIT_F ),
614 .INIT_FILE (INIT_FILE )
615 ) RAM (
616 .RDATA(RDATA),
617 .RCLK (RCLK ),
618 .RCLKE(RCLKE),
619 .RE (RE ),
620 .RADDR(RADDR),
621 .WCLK (~WCLKN),
622 .WCLKE(WCLKE),
623 .WE (WE ),
624 .WADDR(WADDR),
625 .MASK (MASK ),
626 .WDATA(WDATA)
627 );
628 endmodule
629
630 module SB_RAM40_4KNRNW (
631 (* abc_flop_q *) output [15:0] RDATA,
632 input RCLKN, RCLKE, RE,
633 input [10:0] RADDR,
634 input WCLKN, WCLKE, WE,
635 input [10:0] WADDR,
636 input [15:0] MASK, WDATA
637 );
638 parameter WRITE_MODE = 0;
639 parameter READ_MODE = 0;
640
641 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
642 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
643 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
644 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
645 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
646 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
647 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
648 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
649 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
650 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
651 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
652 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
653 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
654 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
655 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
656 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
657
658 parameter INIT_FILE = "";
659
660 SB_RAM40_4K #(
661 .WRITE_MODE(WRITE_MODE),
662 .READ_MODE (READ_MODE ),
663 .INIT_0 (INIT_0 ),
664 .INIT_1 (INIT_1 ),
665 .INIT_2 (INIT_2 ),
666 .INIT_3 (INIT_3 ),
667 .INIT_4 (INIT_4 ),
668 .INIT_5 (INIT_5 ),
669 .INIT_6 (INIT_6 ),
670 .INIT_7 (INIT_7 ),
671 .INIT_8 (INIT_8 ),
672 .INIT_9 (INIT_9 ),
673 .INIT_A (INIT_A ),
674 .INIT_B (INIT_B ),
675 .INIT_C (INIT_C ),
676 .INIT_D (INIT_D ),
677 .INIT_E (INIT_E ),
678 .INIT_F (INIT_F ),
679 .INIT_FILE (INIT_FILE )
680 ) RAM (
681 .RDATA(RDATA),
682 .RCLK (~RCLKN),
683 .RCLKE(RCLKE),
684 .RE (RE ),
685 .RADDR(RADDR),
686 .WCLK (~WCLKN),
687 .WCLKE(WCLKE),
688 .WE (WE ),
689 .WADDR(WADDR),
690 .MASK (MASK ),
691 .WDATA(WDATA)
692 );
693 endmodule
694
695 // Packed IceStorm Logic Cells
696
697 module ICESTORM_LC (
698 input I0, I1, I2, I3, CIN, CLK, CEN, SR,
699 output LO, O, COUT
700 );
701 parameter [15:0] LUT_INIT = 0;
702
703 parameter [0:0] NEG_CLK = 0;
704 parameter [0:0] CARRY_ENABLE = 0;
705 parameter [0:0] DFF_ENABLE = 0;
706 parameter [0:0] SET_NORESET = 0;
707 parameter [0:0] ASYNC_SR = 0;
708
709 parameter [0:0] CIN_CONST = 0;
710 parameter [0:0] CIN_SET = 0;
711
712 wire mux_cin = CIN_CONST ? CIN_SET : CIN;
713
714 assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && mux_cin) : 1'bx;
715
716 wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
717 wire [3:0] lut_s2 = I2 ? lut_s3[ 7:4] : lut_s3[3:0];
718 wire [1:0] lut_s1 = I1 ? lut_s2[ 3:2] : lut_s2[1:0];
719 wire lut_o = I0 ? lut_s1[ 1] : lut_s1[ 0];
720
721 assign LO = lut_o;
722
723 wire polarized_clk;
724 assign polarized_clk = CLK ^ NEG_CLK;
725
726 reg o_reg;
727 always @(posedge polarized_clk)
728 if (CEN)
729 o_reg <= SR ? SET_NORESET : lut_o;
730
731 reg o_reg_async;
732 always @(posedge polarized_clk, posedge SR)
733 if (SR)
734 o_reg <= SET_NORESET;
735 else if (CEN)
736 o_reg <= lut_o;
737
738 assign O = DFF_ENABLE ? ASYNC_SR ? o_reg_async : o_reg : lut_o;
739 endmodule
740
741 // SiliconBlue PLL Cells
742
743 (* blackbox *)
744 module SB_PLL40_CORE (
745 input REFERENCECLK,
746 output PLLOUTCORE,
747 output PLLOUTGLOBAL,
748 input EXTFEEDBACK,
749 input [7:0] DYNAMICDELAY,
750 output LOCK,
751 input BYPASS,
752 input RESETB,
753 input LATCHINPUTVALUE,
754 output SDO,
755 input SDI,
756 input SCLK
757 );
758 parameter FEEDBACK_PATH = "SIMPLE";
759 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
760 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
761 parameter SHIFTREG_DIV_MODE = 1'b0;
762 parameter FDA_FEEDBACK = 4'b0000;
763 parameter FDA_RELATIVE = 4'b0000;
764 parameter PLLOUT_SELECT = "GENCLK";
765 parameter DIVR = 4'b0000;
766 parameter DIVF = 7'b0000000;
767 parameter DIVQ = 3'b000;
768 parameter FILTER_RANGE = 3'b000;
769 parameter ENABLE_ICEGATE = 1'b0;
770 parameter TEST_MODE = 1'b0;
771 parameter EXTERNAL_DIVIDE_FACTOR = 1;
772 endmodule
773
774 (* blackbox *)
775 module SB_PLL40_PAD (
776 input PACKAGEPIN,
777 output PLLOUTCORE,
778 output PLLOUTGLOBAL,
779 input EXTFEEDBACK,
780 input [7:0] DYNAMICDELAY,
781 output LOCK,
782 input BYPASS,
783 input RESETB,
784 input LATCHINPUTVALUE,
785 output SDO,
786 input SDI,
787 input SCLK
788 );
789 parameter FEEDBACK_PATH = "SIMPLE";
790 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
791 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
792 parameter SHIFTREG_DIV_MODE = 1'b0;
793 parameter FDA_FEEDBACK = 4'b0000;
794 parameter FDA_RELATIVE = 4'b0000;
795 parameter PLLOUT_SELECT = "GENCLK";
796 parameter DIVR = 4'b0000;
797 parameter DIVF = 7'b0000000;
798 parameter DIVQ = 3'b000;
799 parameter FILTER_RANGE = 3'b000;
800 parameter ENABLE_ICEGATE = 1'b0;
801 parameter TEST_MODE = 1'b0;
802 parameter EXTERNAL_DIVIDE_FACTOR = 1;
803 endmodule
804
805 (* blackbox *)
806 module SB_PLL40_2_PAD (
807 input PACKAGEPIN,
808 output PLLOUTCOREA,
809 output PLLOUTGLOBALA,
810 output PLLOUTCOREB,
811 output PLLOUTGLOBALB,
812 input EXTFEEDBACK,
813 input [7:0] DYNAMICDELAY,
814 output LOCK,
815 input BYPASS,
816 input RESETB,
817 input LATCHINPUTVALUE,
818 output SDO,
819 input SDI,
820 input SCLK
821 );
822 parameter FEEDBACK_PATH = "SIMPLE";
823 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
824 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
825 parameter SHIFTREG_DIV_MODE = 1'b0;
826 parameter FDA_FEEDBACK = 4'b0000;
827 parameter FDA_RELATIVE = 4'b0000;
828 parameter PLLOUT_SELECT_PORTB = "GENCLK";
829 parameter DIVR = 4'b0000;
830 parameter DIVF = 7'b0000000;
831 parameter DIVQ = 3'b000;
832 parameter FILTER_RANGE = 3'b000;
833 parameter ENABLE_ICEGATE_PORTA = 1'b0;
834 parameter ENABLE_ICEGATE_PORTB = 1'b0;
835 parameter TEST_MODE = 1'b0;
836 parameter EXTERNAL_DIVIDE_FACTOR = 1;
837 endmodule
838
839 (* blackbox *)
840 module SB_PLL40_2F_CORE (
841 input REFERENCECLK,
842 output PLLOUTCOREA,
843 output PLLOUTGLOBALA,
844 output PLLOUTCOREB,
845 output PLLOUTGLOBALB,
846 input EXTFEEDBACK,
847 input [7:0] DYNAMICDELAY,
848 output LOCK,
849 input BYPASS,
850 input RESETB,
851 input LATCHINPUTVALUE,
852 output SDO,
853 input SDI,
854 input SCLK
855 );
856 parameter FEEDBACK_PATH = "SIMPLE";
857 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
858 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
859 parameter SHIFTREG_DIV_MODE = 1'b0;
860 parameter FDA_FEEDBACK = 4'b0000;
861 parameter FDA_RELATIVE = 4'b0000;
862 parameter PLLOUT_SELECT_PORTA = "GENCLK";
863 parameter PLLOUT_SELECT_PORTB = "GENCLK";
864 parameter DIVR = 4'b0000;
865 parameter DIVF = 7'b0000000;
866 parameter DIVQ = 3'b000;
867 parameter FILTER_RANGE = 3'b000;
868 parameter ENABLE_ICEGATE_PORTA = 1'b0;
869 parameter ENABLE_ICEGATE_PORTB = 1'b0;
870 parameter TEST_MODE = 1'b0;
871 parameter EXTERNAL_DIVIDE_FACTOR = 1;
872 endmodule
873
874 (* blackbox *)
875 module SB_PLL40_2F_PAD (
876 input PACKAGEPIN,
877 output PLLOUTCOREA,
878 output PLLOUTGLOBALA,
879 output PLLOUTCOREB,
880 output PLLOUTGLOBALB,
881 input EXTFEEDBACK,
882 input [7:0] DYNAMICDELAY,
883 output LOCK,
884 input BYPASS,
885 input RESETB,
886 input LATCHINPUTVALUE,
887 output SDO,
888 input SDI,
889 input SCLK
890 );
891 parameter FEEDBACK_PATH = "SIMPLE";
892 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
893 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
894 parameter SHIFTREG_DIV_MODE = 2'b00;
895 parameter FDA_FEEDBACK = 4'b0000;
896 parameter FDA_RELATIVE = 4'b0000;
897 parameter PLLOUT_SELECT_PORTA = "GENCLK";
898 parameter PLLOUT_SELECT_PORTB = "GENCLK";
899 parameter DIVR = 4'b0000;
900 parameter DIVF = 7'b0000000;
901 parameter DIVQ = 3'b000;
902 parameter FILTER_RANGE = 3'b000;
903 parameter ENABLE_ICEGATE_PORTA = 1'b0;
904 parameter ENABLE_ICEGATE_PORTB = 1'b0;
905 parameter TEST_MODE = 1'b0;
906 parameter EXTERNAL_DIVIDE_FACTOR = 1;
907 endmodule
908
909 // SiliconBlue Device Configuration Cells
910
911 (* blackbox, keep *)
912 module SB_WARMBOOT (
913 input BOOT,
914 input S1,
915 input S0
916 );
917 endmodule
918
919 (* nomem2reg *)
920 module SB_SPRAM256KA (
921 input [13:0] ADDRESS,
922 input [15:0] DATAIN,
923 input [3:0] MASKWREN,
924 input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
925 (* abc_flop_q *) output reg [15:0] DATAOUT
926 );
927 `ifndef BLACKBOX
928 `ifndef EQUIV
929 reg [15:0] mem [0:16383];
930 wire off = SLEEP || !POWEROFF;
931 integer i;
932
933 always @(negedge POWEROFF) begin
934 for (i = 0; i <= 16383; i = i+1)
935 mem[i] = 'bx;
936 end
937
938 always @(posedge CLOCK, posedge off) begin
939 if (off) begin
940 DATAOUT <= 0;
941 end else
942 if (CHIPSELECT && !STANDBY && !WREN) begin
943 DATAOUT <= mem[ADDRESS];
944 end else begin
945 if (CHIPSELECT && !STANDBY && WREN) begin
946 if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0];
947 if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4];
948 if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8];
949 if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12];
950 end
951 DATAOUT <= 'bx;
952 end
953 end
954 `endif
955 `endif
956 endmodule
957
958 (* blackbox *)
959 module SB_HFOSC(
960 input TRIM0,
961 input TRIM1,
962 input TRIM2,
963 input TRIM3,
964 input TRIM4,
965 input TRIM5,
966 input TRIM6,
967 input TRIM7,
968 input TRIM8,
969 input TRIM9,
970 input CLKHFPU,
971 input CLKHFEN,
972 output CLKHF
973 );
974 parameter TRIM_EN = "0b0";
975 parameter CLKHF_DIV = "0b00";
976 endmodule
977
978 (* blackbox *)
979 module SB_LFOSC(
980 input CLKLFPU,
981 input CLKLFEN,
982 output CLKLF
983 );
984 endmodule
985
986 (* blackbox *)
987 module SB_RGBA_DRV(
988 input CURREN,
989 input RGBLEDEN,
990 input RGB0PWM,
991 input RGB1PWM,
992 input RGB2PWM,
993 output RGB0,
994 output RGB1,
995 output RGB2
996 );
997 parameter CURRENT_MODE = "0b0";
998 parameter RGB0_CURRENT = "0b000000";
999 parameter RGB1_CURRENT = "0b000000";
1000 parameter RGB2_CURRENT = "0b000000";
1001 endmodule
1002
1003 (* blackbox *)
1004 module SB_LED_DRV_CUR(
1005 input EN,
1006 output LEDPU
1007 );
1008 endmodule
1009
1010 (* blackbox *)
1011 module SB_RGB_DRV(
1012 input RGBLEDEN,
1013 input RGB0PWM,
1014 input RGB1PWM,
1015 input RGB2PWM,
1016 input RGBPU,
1017 output RGB0,
1018 output RGB1,
1019 output RGB2
1020 );
1021 parameter CURRENT_MODE = "0b0";
1022 parameter RGB0_CURRENT = "0b000000";
1023 parameter RGB1_CURRENT = "0b000000";
1024 parameter RGB2_CURRENT = "0b000000";
1025 endmodule
1026
1027 (* blackbox *)
1028 module SB_I2C(
1029 input SBCLKI,
1030 input SBRWI,
1031 input SBSTBI,
1032 input SBADRI7,
1033 input SBADRI6,
1034 input SBADRI5,
1035 input SBADRI4,
1036 input SBADRI3,
1037 input SBADRI2,
1038 input SBADRI1,
1039 input SBADRI0,
1040 input SBDATI7,
1041 input SBDATI6,
1042 input SBDATI5,
1043 input SBDATI4,
1044 input SBDATI3,
1045 input SBDATI2,
1046 input SBDATI1,
1047 input SBDATI0,
1048 input SCLI,
1049 input SDAI,
1050 output SBDATO7,
1051 output SBDATO6,
1052 output SBDATO5,
1053 output SBDATO4,
1054 output SBDATO3,
1055 output SBDATO2,
1056 output SBDATO1,
1057 output SBDATO0,
1058 output SBACKO,
1059 output I2CIRQ,
1060 output I2CWKUP,
1061 output SCLO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
1062 output SCLOE,
1063 output SDAO,
1064 output SDAOE
1065 );
1066 parameter I2C_SLAVE_INIT_ADDR = "0b1111100001";
1067 parameter BUS_ADDR74 = "0b0001";
1068 endmodule
1069
1070 (* blackbox *)
1071 module SB_SPI (
1072 input SBCLKI,
1073 input SBRWI,
1074 input SBSTBI,
1075 input SBADRI7,
1076 input SBADRI6,
1077 input SBADRI5,
1078 input SBADRI4,
1079 input SBADRI3,
1080 input SBADRI2,
1081 input SBADRI1,
1082 input SBADRI0,
1083 input SBDATI7,
1084 input SBDATI6,
1085 input SBDATI5,
1086 input SBDATI4,
1087 input SBDATI3,
1088 input SBDATI2,
1089 input SBDATI1,
1090 input SBDATI0,
1091 input MI,
1092 input SI,
1093 input SCKI,
1094 input SCSNI,
1095 output SBDATO7,
1096 output SBDATO6,
1097 output SBDATO5,
1098 output SBDATO4,
1099 output SBDATO3,
1100 output SBDATO2,
1101 output SBDATO1,
1102 output SBDATO0,
1103 output SBACKO,
1104 output SPIIRQ,
1105 output SPIWKUP,
1106 output SO,
1107 output SOE,
1108 output MO,
1109 output MOE,
1110 output SCKO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
1111 output SCKOE,
1112 output MCSNO3,
1113 output MCSNO2,
1114 output MCSNO1,
1115 output MCSNO0,
1116 output MCSNOE3,
1117 output MCSNOE2,
1118 output MCSNOE1,
1119 output MCSNOE0
1120 );
1121 parameter BUS_ADDR74 = "0b0000";
1122 endmodule
1123
1124 (* blackbox *)
1125 module SB_LEDDA_IP(
1126 input LEDDCS,
1127 input LEDDCLK,
1128 input LEDDDAT7,
1129 input LEDDDAT6,
1130 input LEDDDAT5,
1131 input LEDDDAT4,
1132 input LEDDDAT3,
1133 input LEDDDAT2,
1134 input LEDDDAT1,
1135 input LEDDDAT0,
1136 input LEDDADDR3,
1137 input LEDDADDR2,
1138 input LEDDADDR1,
1139 input LEDDADDR0,
1140 input LEDDDEN,
1141 input LEDDEXE,
1142 input LEDDRST,
1143 output PWMOUT0,
1144 output PWMOUT1,
1145 output PWMOUT2,
1146 output LEDDON
1147 );
1148 endmodule
1149
1150 (* blackbox *)
1151 module SB_FILTER_50NS(
1152 input FILTERIN,
1153 output FILTEROUT
1154 );
1155 endmodule
1156
1157 module SB_IO_I3C (
1158 inout PACKAGE_PIN,
1159 input LATCH_INPUT_VALUE,
1160 input CLOCK_ENABLE,
1161 input INPUT_CLK,
1162 input OUTPUT_CLK,
1163 input OUTPUT_ENABLE,
1164 input D_OUT_0,
1165 input D_OUT_1,
1166 output D_IN_0,
1167 output D_IN_1,
1168 input PU_ENB,
1169 input WEAK_PU_ENB
1170 );
1171 parameter [5:0] PIN_TYPE = 6'b000000;
1172 parameter [0:0] PULLUP = 1'b0;
1173 parameter [0:0] WEAK_PULLUP = 1'b0;
1174 parameter [0:0] NEG_TRIGGER = 1'b0;
1175 parameter IO_STANDARD = "SB_LVCMOS";
1176
1177 `ifndef BLACKBOX
1178 reg dout, din_0, din_1;
1179 reg din_q_0, din_q_1;
1180 reg dout_q_0, dout_q_1;
1181 reg outena_q;
1182
1183 generate if (!NEG_TRIGGER) begin
1184 always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
1185 always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
1186 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
1187 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
1188 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
1189 end else begin
1190 always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
1191 always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
1192 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
1193 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
1194 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
1195 end endgenerate
1196
1197 always @* begin
1198 if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
1199 din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
1200 din_1 = din_q_1;
1201 end
1202
1203 // work around simulation glitches on dout in DDR mode
1204 reg outclk_delayed_1;
1205 reg outclk_delayed_2;
1206 always @* outclk_delayed_1 <= OUTPUT_CLK;
1207 always @* outclk_delayed_2 <= outclk_delayed_1;
1208
1209 always @* begin
1210 if (PIN_TYPE[3])
1211 dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
1212 else
1213 dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
1214 end
1215
1216 assign D_IN_0 = din_0, D_IN_1 = din_1;
1217
1218 generate
1219 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
1220 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
1221 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
1222 endgenerate
1223 `endif
1224 endmodule
1225
1226 module SB_IO_OD (
1227 inout PACKAGEPIN,
1228 input LATCHINPUTVALUE,
1229 input CLOCKENABLE,
1230 input INPUTCLK,
1231 input OUTPUTCLK,
1232 input OUTPUTENABLE,
1233 input DOUT1,
1234 input DOUT0,
1235 output DIN1,
1236 output DIN0
1237 );
1238 parameter [5:0] PIN_TYPE = 6'b000000;
1239 parameter [0:0] NEG_TRIGGER = 1'b0;
1240
1241 `ifndef BLACKBOX
1242 reg dout, din_0, din_1;
1243 reg din_q_0, din_q_1;
1244 reg dout_q_0, dout_q_1;
1245 reg outena_q;
1246
1247 generate if (!NEG_TRIGGER) begin
1248 always @(posedge INPUTCLK) if (CLOCKENABLE) din_q_0 <= PACKAGEPIN;
1249 always @(negedge INPUTCLK) if (CLOCKENABLE) din_q_1 <= PACKAGEPIN;
1250 always @(posedge OUTPUTCLK) if (CLOCKENABLE) dout_q_0 <= DOUT0;
1251 always @(negedge OUTPUTCLK) if (CLOCKENABLE) dout_q_1 <= DOUT1;
1252 always @(posedge OUTPUTCLK) if (CLOCKENABLE) outena_q <= OUTPUTENABLE;
1253 end else begin
1254 always @(negedge INPUTCLK) if (CLOCKENABLE) din_q_0 <= PACKAGEPIN;
1255 always @(posedge INPUTCLK) if (CLOCKENABLE) din_q_1 <= PACKAGEPIN;
1256 always @(negedge OUTPUTCLK) if (CLOCKENABLE) dout_q_0 <= DOUT0;
1257 always @(posedge OUTPUTCLK) if (CLOCKENABLE) dout_q_1 <= DOUT1;
1258 always @(negedge OUTPUTCLK) if (CLOCKENABLE) outena_q <= OUTPUTENABLE;
1259 end endgenerate
1260
1261 always @* begin
1262 if (!PIN_TYPE[1] || !LATCHINPUTVALUE)
1263 din_0 = PIN_TYPE[0] ? PACKAGEPIN : din_q_0;
1264 din_1 = din_q_1;
1265 end
1266
1267 // work around simulation glitches on dout in DDR mode
1268 reg outclk_delayed_1;
1269 reg outclk_delayed_2;
1270 always @* outclk_delayed_1 <= OUTPUTCLK;
1271 always @* outclk_delayed_2 <= outclk_delayed_1;
1272
1273 always @* begin
1274 if (PIN_TYPE[3])
1275 dout = PIN_TYPE[2] ? !dout_q_0 : DOUT0;
1276 else
1277 dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
1278 end
1279
1280 assign DIN0 = din_0, DIN1 = din_1;
1281
1282 generate
1283 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGEPIN = dout ? 1'bz : 1'b0;
1284 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGEPIN = OUTPUTENABLE ? (dout ? 1'bz : 1'b0) : 1'bz;
1285 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGEPIN = outena_q ? (dout ? 1'bz : 1'b0) : 1'bz;
1286 endgenerate
1287 `endif
1288 endmodule
1289
1290 module SB_MAC16 (
1291 input CLK, CE,
1292 input [15:0] C, A, B, D,
1293 input AHOLD, BHOLD, CHOLD, DHOLD,
1294 input IRSTTOP, IRSTBOT,
1295 input ORSTTOP, ORSTBOT,
1296 input OLOADTOP, OLOADBOT,
1297 input ADDSUBTOP, ADDSUBBOT,
1298 input OHOLDTOP, OHOLDBOT,
1299 input CI, ACCUMCI, SIGNEXTIN,
1300 output [31:0] O,
1301 output CO, ACCUMCO, SIGNEXTOUT
1302 );
1303 parameter [0:0] NEG_TRIGGER = 0;
1304 parameter [0:0] C_REG = 0;
1305 parameter [0:0] A_REG = 0;
1306 parameter [0:0] B_REG = 0;
1307 parameter [0:0] D_REG = 0;
1308 parameter [0:0] TOP_8x8_MULT_REG = 0;
1309 parameter [0:0] BOT_8x8_MULT_REG = 0;
1310 parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
1311 parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
1312 parameter [1:0] TOPOUTPUT_SELECT = 0;
1313 parameter [1:0] TOPADDSUB_LOWERINPUT = 0;
1314 parameter [0:0] TOPADDSUB_UPPERINPUT = 0;
1315 parameter [1:0] TOPADDSUB_CARRYSELECT = 0;
1316 parameter [1:0] BOTOUTPUT_SELECT = 0;
1317 parameter [1:0] BOTADDSUB_LOWERINPUT = 0;
1318 parameter [0:0] BOTADDSUB_UPPERINPUT = 0;
1319 parameter [1:0] BOTADDSUB_CARRYSELECT = 0;
1320 parameter [0:0] MODE_8x8 = 0;
1321 parameter [0:0] A_SIGNED = 0;
1322 parameter [0:0] B_SIGNED = 0;
1323
1324 wire clock = CLK ^ NEG_TRIGGER;
1325
1326 // internal wires, compare Figure on page 133 of ICE Technology Library 3.0 and Fig 2 on page 2 of Lattice TN1295-DSP
1327 // http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201608.pdf
1328 // https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/AD/DSPFunctionUsageGuideforICE40Devices.ashx
1329 wire [15:0] iA, iB, iC, iD;
1330 wire [15:0] iF, iJ, iK, iG;
1331 wire [31:0] iL, iH;
1332 wire [15:0] iW, iX, iP, iQ;
1333 wire [15:0] iY, iZ, iR, iS;
1334 wire HCI, LCI, LCO;
1335
1336 // Regs C and A
1337 reg [15:0] rC, rA;
1338 always @(posedge clock, posedge IRSTTOP) begin
1339 if (IRSTTOP) begin
1340 rC <= 0;
1341 rA <= 0;
1342 end else if (CE) begin
1343 if (!CHOLD) rC <= C;
1344 if (!AHOLD) rA <= A;
1345 end
1346 end
1347 assign iC = C_REG ? rC : C;
1348 assign iA = A_REG ? rA : A;
1349
1350 // Regs B and D
1351 reg [15:0] rB, rD;
1352 always @(posedge clock, posedge IRSTBOT) begin
1353 if (IRSTBOT) begin
1354 rB <= 0;
1355 rD <= 0;
1356 end else if (CE) begin
1357 if (!BHOLD) rB <= B;
1358 if (!DHOLD) rD <= D;
1359 end
1360 end
1361 assign iB = B_REG ? rB : B;
1362 assign iD = D_REG ? rD : D;
1363
1364 // Multiplier Stage
1365 wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
1366 wire [15:0] Ah, Al, Bh, Bl;
1367 assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]};
1368 assign Al = {A_SIGNED ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
1369 assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]};
1370 assign Bl = {B_SIGNED ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
1371 assign p_Ah_Bh = Ah * Bh;
1372 assign p_Al_Bh = Al * Bh;
1373 assign p_Ah_Bl = Ah * Bl;
1374 assign p_Al_Bl = Al * Bl;
1375
1376 // Regs F and J
1377 reg [15:0] rF, rJ;
1378 always @(posedge clock, posedge IRSTTOP) begin
1379 if (IRSTTOP) begin
1380 rF <= 0;
1381 rJ <= 0;
1382 end else if (CE) begin
1383 rF <= p_Ah_Bh;
1384 if (!MODE_8x8) rJ <= p_Al_Bh;
1385 end
1386 end
1387 assign iF = TOP_8x8_MULT_REG ? rF : p_Ah_Bh;
1388 assign iJ = PIPELINE_16x16_MULT_REG1 ? rJ : p_Al_Bh;
1389
1390 // Regs K and G
1391 reg [15:0] rK, rG;
1392 always @(posedge clock, posedge IRSTBOT) begin
1393 if (IRSTBOT) begin
1394 rK <= 0;
1395 rG <= 0;
1396 end else if (CE) begin
1397 if (!MODE_8x8) rK <= p_Ah_Bl;
1398 rG <= p_Al_Bl;
1399 end
1400 end
1401 assign iK = PIPELINE_16x16_MULT_REG1 ? rK : p_Ah_Bl;
1402 assign iG = BOT_8x8_MULT_REG ? rG : p_Al_Bl;
1403
1404 // Adder Stage
1405 assign iL = iG + (iK << 8) + (iJ << 8) + (iF << 16);
1406
1407 // Reg H
1408 reg [31:0] rH;
1409 always @(posedge clock, posedge IRSTBOT) begin
1410 if (IRSTBOT) begin
1411 rH <= 0;
1412 end else if (CE) begin
1413 if (!MODE_8x8) rH <= iL;
1414 end
1415 end
1416 assign iH = PIPELINE_16x16_MULT_REG2 ? rH : iL;
1417
1418 // Hi Output Stage
1419 wire [15:0] XW, Oh;
1420 reg [15:0] rQ;
1421 assign iW = TOPADDSUB_UPPERINPUT ? iC : iQ;
1422 assign iX = (TOPADDSUB_LOWERINPUT == 0) ? iA : (TOPADDSUB_LOWERINPUT == 1) ? iF : (TOPADDSUB_LOWERINPUT == 2) ? iH[31:16] : {16{iZ[15]}};
1423 assign {ACCUMCO, XW} = iX + (iW ^ {16{ADDSUBTOP}}) + HCI;
1424 assign CO = ACCUMCO ^ ADDSUBTOP;
1425 assign iP = OLOADTOP ? iC : XW ^ {16{ADDSUBTOP}};
1426 always @(posedge clock, posedge ORSTTOP) begin
1427 if (ORSTTOP) begin
1428 rQ <= 0;
1429 end else if (CE) begin
1430 if (!OHOLDTOP) rQ <= iP;
1431 end
1432 end
1433 assign iQ = rQ;
1434 assign Oh = (TOPOUTPUT_SELECT == 0) ? iP : (TOPOUTPUT_SELECT == 1) ? iQ : (TOPOUTPUT_SELECT == 2) ? iF : iH[31:16];
1435 assign HCI = (TOPADDSUB_CARRYSELECT == 0) ? 1'b0 : (TOPADDSUB_CARRYSELECT == 1) ? 1'b1 : (TOPADDSUB_CARRYSELECT == 2) ? LCO : LCO ^ ADDSUBBOT;
1436 assign SIGNEXTOUT = iX[15];
1437
1438 // Lo Output Stage
1439 wire [15:0] YZ, Ol;
1440 reg [15:0] rS;
1441 assign iY = BOTADDSUB_UPPERINPUT ? iD : iS;
1442 assign iZ = (BOTADDSUB_LOWERINPUT == 0) ? iB : (BOTADDSUB_LOWERINPUT == 1) ? iG : (BOTADDSUB_LOWERINPUT == 2) ? iH[15:0] : {16{SIGNEXTIN}};
1443 assign {LCO, YZ} = iZ + (iY ^ {16{ADDSUBBOT}}) + LCI;
1444 assign iR = OLOADBOT ? iD : YZ ^ {16{ADDSUBBOT}};
1445 always @(posedge clock, posedge ORSTBOT) begin
1446 if (ORSTBOT) begin
1447 rS <= 0;
1448 end else if (CE) begin
1449 if (!OHOLDBOT) rS <= iR;
1450 end
1451 end
1452 assign iS = rS;
1453 assign Ol = (BOTOUTPUT_SELECT == 0) ? iR : (BOTOUTPUT_SELECT == 1) ? iS : (BOTOUTPUT_SELECT == 2) ? iG : iH[15:0];
1454 assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI;
1455 assign O = {Oh, Ol};
1456 endmodule