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Merge pull request #1112 from acw1251/pyosys_sigsig_issue
[yosys.git] / techlibs / ice40 / cells_sim.v
1
2 `define SB_DFF_REG reg Q = 0
3 // `define SB_DFF_REG reg Q
4
5 // SiliconBlue IO Cells
6
7 module SB_IO (
8 inout PACKAGE_PIN,
9 input LATCH_INPUT_VALUE,
10 input CLOCK_ENABLE,
11 input INPUT_CLK,
12 input OUTPUT_CLK,
13 input OUTPUT_ENABLE,
14 input D_OUT_0,
15 input D_OUT_1,
16 output D_IN_0,
17 output D_IN_1
18 );
19 parameter [5:0] PIN_TYPE = 6'b000000;
20 parameter [0:0] PULLUP = 1'b0;
21 parameter [0:0] NEG_TRIGGER = 1'b0;
22 parameter IO_STANDARD = "SB_LVCMOS";
23
24 `ifndef BLACKBOX
25 reg dout, din_0, din_1;
26 reg din_q_0, din_q_1;
27 reg dout_q_0, dout_q_1;
28 reg outena_q;
29
30 // IO tile generates a constant 1'b1 internally if global_cen is not connected
31 wire clken_pulled = CLOCK_ENABLE || CLOCK_ENABLE === 1'bz;
32 reg clken_pulled_ri;
33 reg clken_pulled_ro;
34
35 generate if (!NEG_TRIGGER) begin
36 always @(posedge INPUT_CLK) clken_pulled_ri <= clken_pulled;
37 always @(posedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN;
38 always @(negedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN;
39 always @(posedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled;
40 always @(posedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0;
41 always @(negedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1;
42 always @(posedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE;
43 end else begin
44 always @(negedge INPUT_CLK) clken_pulled_ri <= clken_pulled;
45 always @(negedge INPUT_CLK) if (clken_pulled) din_q_0 <= PACKAGE_PIN;
46 always @(posedge INPUT_CLK) if (clken_pulled_ri) din_q_1 <= PACKAGE_PIN;
47 always @(negedge OUTPUT_CLK) clken_pulled_ro <= clken_pulled;
48 always @(negedge OUTPUT_CLK) if (clken_pulled) dout_q_0 <= D_OUT_0;
49 always @(posedge OUTPUT_CLK) if (clken_pulled_ro) dout_q_1 <= D_OUT_1;
50 always @(negedge OUTPUT_CLK) if (clken_pulled) outena_q <= OUTPUT_ENABLE;
51 end endgenerate
52
53 always @* begin
54 if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
55 din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
56 din_1 = din_q_1;
57 end
58
59 // work around simulation glitches on dout in DDR mode
60 reg outclk_delayed_1;
61 reg outclk_delayed_2;
62 always @* outclk_delayed_1 <= OUTPUT_CLK;
63 always @* outclk_delayed_2 <= outclk_delayed_1;
64
65 always @* begin
66 if (PIN_TYPE[3])
67 dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
68 else
69 dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
70 end
71
72 assign D_IN_0 = din_0, D_IN_1 = din_1;
73
74 generate
75 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
76 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
77 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
78 endgenerate
79 `endif
80 endmodule
81
82 module SB_GB_IO (
83 inout PACKAGE_PIN,
84 output GLOBAL_BUFFER_OUTPUT,
85 input LATCH_INPUT_VALUE,
86 input CLOCK_ENABLE,
87 input INPUT_CLK,
88 input OUTPUT_CLK,
89 input OUTPUT_ENABLE,
90 input D_OUT_0,
91 input D_OUT_1,
92 output D_IN_0,
93 output D_IN_1
94 );
95 parameter [5:0] PIN_TYPE = 6'b000000;
96 parameter [0:0] PULLUP = 1'b0;
97 parameter [0:0] NEG_TRIGGER = 1'b0;
98 parameter IO_STANDARD = "SB_LVCMOS";
99
100 assign GLOBAL_BUFFER_OUTPUT = PACKAGE_PIN;
101
102 SB_IO #(
103 .PIN_TYPE(PIN_TYPE),
104 .PULLUP(PULLUP),
105 .NEG_TRIGGER(NEG_TRIGGER),
106 .IO_STANDARD(IO_STANDARD)
107 ) IO (
108 .PACKAGE_PIN(PACKAGE_PIN),
109 .LATCH_INPUT_VALUE(LATCH_INPUT_VALUE),
110 .CLOCK_ENABLE(CLOCK_ENABLE),
111 .INPUT_CLK(INPUT_CLK),
112 .OUTPUT_CLK(OUTPUT_CLK),
113 .OUTPUT_ENABLE(OUTPUT_ENABLE),
114 .D_OUT_0(D_OUT_0),
115 .D_OUT_1(D_OUT_1),
116 .D_IN_0(D_IN_0),
117 .D_IN_1(D_IN_1)
118 );
119 endmodule
120
121 module SB_GB (
122 input USER_SIGNAL_TO_GLOBAL_BUFFER,
123 output GLOBAL_BUFFER_OUTPUT
124 );
125 assign GLOBAL_BUFFER_OUTPUT = USER_SIGNAL_TO_GLOBAL_BUFFER;
126 endmodule
127
128 // SiliconBlue Logic Cells
129
130 (* lib_whitebox *)
131 module SB_LUT4 (output O, input I0, I1, I2, I3);
132 parameter [15:0] LUT_INIT = 0;
133 wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
134 wire [3:0] s2 = I2 ? s3[ 7:4] : s3[3:0];
135 wire [1:0] s1 = I1 ? s2[ 3:2] : s2[1:0];
136 assign O = I0 ? s1[1] : s1[0];
137 endmodule
138
139 (* lib_whitebox *)
140 module SB_CARRY (output CO, input I0, I1, CI);
141 assign CO = (I0 && I1) || ((I0 || I1) && CI);
142 endmodule
143
144 (* abc_box_id = 1, lib_whitebox *)
145 module \$__ICE40_FULL_ADDER (
146 (* abc_carry *)
147 output CO,
148 output O,
149 input A,
150 input B,
151 (* abc_carry *)
152 input CI
153 );
154 SB_CARRY carry (
155 .I0(A),
156 .I1(B),
157 .CI(CI),
158 .CO(CO)
159 );
160 SB_LUT4 #(
161 // I0: 1010 1010 1010 1010
162 // I1: 1100 1100 1100 1100
163 // I2: 1111 0000 1111 0000
164 // I3: 1111 1111 0000 0000
165 .LUT_INIT(16'b 0110_1001_1001_0110)
166 ) adder (
167 .I0(1'b0),
168 .I1(A),
169 .I2(B),
170 .I3(CI),
171 .O(O)
172 );
173 endmodule
174
175 // Positive Edge SiliconBlue FF Cells
176
177 module SB_DFF (output `SB_DFF_REG, input C, D);
178 always @(posedge C)
179 Q <= D;
180 endmodule
181
182 module SB_DFFE (output `SB_DFF_REG, input C, E, D);
183 always @(posedge C)
184 if (E)
185 Q <= D;
186 endmodule
187
188 module SB_DFFSR (output `SB_DFF_REG, input C, R, D);
189 always @(posedge C)
190 if (R)
191 Q <= 0;
192 else
193 Q <= D;
194 endmodule
195
196 module SB_DFFR (output `SB_DFF_REG, input C, R, D);
197 always @(posedge C, posedge R)
198 if (R)
199 Q <= 0;
200 else
201 Q <= D;
202 endmodule
203
204 module SB_DFFSS (output `SB_DFF_REG, input C, S, D);
205 always @(posedge C)
206 if (S)
207 Q <= 1;
208 else
209 Q <= D;
210 endmodule
211
212 module SB_DFFS (output `SB_DFF_REG, input C, S, D);
213 always @(posedge C, posedge S)
214 if (S)
215 Q <= 1;
216 else
217 Q <= D;
218 endmodule
219
220 module SB_DFFESR (output `SB_DFF_REG, input C, E, R, D);
221 always @(posedge C)
222 if (E) begin
223 if (R)
224 Q <= 0;
225 else
226 Q <= D;
227 end
228 endmodule
229
230 module SB_DFFER (output `SB_DFF_REG, input C, E, R, D);
231 always @(posedge C, posedge R)
232 if (R)
233 Q <= 0;
234 else if (E)
235 Q <= D;
236 endmodule
237
238 module SB_DFFESS (output `SB_DFF_REG, input C, E, S, D);
239 always @(posedge C)
240 if (E) begin
241 if (S)
242 Q <= 1;
243 else
244 Q <= D;
245 end
246 endmodule
247
248 module SB_DFFES (output `SB_DFF_REG, input C, E, S, D);
249 always @(posedge C, posedge S)
250 if (S)
251 Q <= 1;
252 else if (E)
253 Q <= D;
254 endmodule
255
256 // Negative Edge SiliconBlue FF Cells
257
258 module SB_DFFN (output `SB_DFF_REG, input C, D);
259 always @(negedge C)
260 Q <= D;
261 endmodule
262
263 module SB_DFFNE (output `SB_DFF_REG, input C, E, D);
264 always @(negedge C)
265 if (E)
266 Q <= D;
267 endmodule
268
269 module SB_DFFNSR (output `SB_DFF_REG, input C, R, D);
270 always @(negedge C)
271 if (R)
272 Q <= 0;
273 else
274 Q <= D;
275 endmodule
276
277 module SB_DFFNR (output `SB_DFF_REG, input C, R, D);
278 always @(negedge C, posedge R)
279 if (R)
280 Q <= 0;
281 else
282 Q <= D;
283 endmodule
284
285 module SB_DFFNSS (output `SB_DFF_REG, input C, S, D);
286 always @(negedge C)
287 if (S)
288 Q <= 1;
289 else
290 Q <= D;
291 endmodule
292
293 module SB_DFFNS (output `SB_DFF_REG, input C, S, D);
294 always @(negedge C, posedge S)
295 if (S)
296 Q <= 1;
297 else
298 Q <= D;
299 endmodule
300
301 module SB_DFFNESR (output `SB_DFF_REG, input C, E, R, D);
302 always @(negedge C)
303 if (E) begin
304 if (R)
305 Q <= 0;
306 else
307 Q <= D;
308 end
309 endmodule
310
311 module SB_DFFNER (output `SB_DFF_REG, input C, E, R, D);
312 always @(negedge C, posedge R)
313 if (R)
314 Q <= 0;
315 else if (E)
316 Q <= D;
317 endmodule
318
319 module SB_DFFNESS (output `SB_DFF_REG, input C, E, S, D);
320 always @(negedge C)
321 if (E) begin
322 if (S)
323 Q <= 1;
324 else
325 Q <= D;
326 end
327 endmodule
328
329 module SB_DFFNES (output `SB_DFF_REG, input C, E, S, D);
330 always @(negedge C, posedge S)
331 if (S)
332 Q <= 1;
333 else if (E)
334 Q <= D;
335 endmodule
336
337 // SiliconBlue RAM Cells
338
339 module SB_RAM40_4K (
340 output [15:0] RDATA,
341 input RCLK, RCLKE, RE,
342 input [10:0] RADDR,
343 input WCLK, WCLKE, WE,
344 input [10:0] WADDR,
345 input [15:0] MASK, WDATA
346 );
347 // MODE 0: 256 x 16
348 // MODE 1: 512 x 8
349 // MODE 2: 1024 x 4
350 // MODE 3: 2048 x 2
351 parameter WRITE_MODE = 0;
352 parameter READ_MODE = 0;
353
354 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
355 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
356 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
357 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
358 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
359 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
360 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
361 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
362 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
363 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
364 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
365 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
366 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
367 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
368 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
369 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
370
371 parameter INIT_FILE = "";
372
373 `ifndef BLACKBOX
374 wire [15:0] WMASK_I;
375 wire [15:0] RMASK_I;
376
377 reg [15:0] RDATA_I;
378 wire [15:0] WDATA_I;
379
380 generate
381 case (WRITE_MODE)
382 0: assign WMASK_I = MASK;
383
384 1: assign WMASK_I = WADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
385 WADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
386
387 2: assign WMASK_I = WADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
388 WADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
389 WADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
390 WADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
391
392 3: assign WMASK_I = WADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
393 WADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
394 WADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
395 WADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
396 WADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
397 WADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
398 WADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
399 WADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
400 endcase
401
402 case (READ_MODE)
403 0: assign RMASK_I = 16'b 0000_0000_0000_0000;
404
405 1: assign RMASK_I = RADDR[ 8] == 0 ? 16'b 1010_1010_1010_1010 :
406 RADDR[ 8] == 1 ? 16'b 0101_0101_0101_0101 : 16'bx;
407
408 2: assign RMASK_I = RADDR[ 9:8] == 0 ? 16'b 1110_1110_1110_1110 :
409 RADDR[ 9:8] == 1 ? 16'b 1101_1101_1101_1101 :
410 RADDR[ 9:8] == 2 ? 16'b 1011_1011_1011_1011 :
411 RADDR[ 9:8] == 3 ? 16'b 0111_0111_0111_0111 : 16'bx;
412
413 3: assign RMASK_I = RADDR[10:8] == 0 ? 16'b 1111_1110_1111_1110 :
414 RADDR[10:8] == 1 ? 16'b 1111_1101_1111_1101 :
415 RADDR[10:8] == 2 ? 16'b 1111_1011_1111_1011 :
416 RADDR[10:8] == 3 ? 16'b 1111_0111_1111_0111 :
417 RADDR[10:8] == 4 ? 16'b 1110_1111_1110_1111 :
418 RADDR[10:8] == 5 ? 16'b 1101_1111_1101_1111 :
419 RADDR[10:8] == 6 ? 16'b 1011_1111_1011_1111 :
420 RADDR[10:8] == 7 ? 16'b 0111_1111_0111_1111 : 16'bx;
421 endcase
422
423 case (WRITE_MODE)
424 0: assign WDATA_I = WDATA;
425
426 1: assign WDATA_I = {WDATA[14], WDATA[14], WDATA[12], WDATA[12],
427 WDATA[10], WDATA[10], WDATA[ 8], WDATA[ 8],
428 WDATA[ 6], WDATA[ 6], WDATA[ 4], WDATA[ 4],
429 WDATA[ 2], WDATA[ 2], WDATA[ 0], WDATA[ 0]};
430
431 2: assign WDATA_I = {WDATA[13], WDATA[13], WDATA[13], WDATA[13],
432 WDATA[ 9], WDATA[ 9], WDATA[ 9], WDATA[ 9],
433 WDATA[ 5], WDATA[ 5], WDATA[ 5], WDATA[ 5],
434 WDATA[ 1], WDATA[ 1], WDATA[ 1], WDATA[ 1]};
435
436 3: assign WDATA_I = {WDATA[11], WDATA[11], WDATA[11], WDATA[11],
437 WDATA[11], WDATA[11], WDATA[11], WDATA[11],
438 WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3],
439 WDATA[ 3], WDATA[ 3], WDATA[ 3], WDATA[ 3]};
440 endcase
441
442 case (READ_MODE)
443 0: assign RDATA = RDATA_I;
444 1: assign RDATA = {1'b0, |RDATA_I[15:14], 1'b0, |RDATA_I[13:12], 1'b0, |RDATA_I[11:10], 1'b0, |RDATA_I[ 9: 8],
445 1'b0, |RDATA_I[ 7: 6], 1'b0, |RDATA_I[ 5: 4], 1'b0, |RDATA_I[ 3: 2], 1'b0, |RDATA_I[ 1: 0]};
446 2: assign RDATA = {2'b0, |RDATA_I[15:12], 3'b0, |RDATA_I[11: 8], 3'b0, |RDATA_I[ 7: 4], 3'b0, |RDATA_I[ 3: 0], 1'b0};
447 3: assign RDATA = {4'b0, |RDATA_I[15: 8], 7'b0, |RDATA_I[ 7: 0], 3'b0};
448 endcase
449 endgenerate
450
451 integer i;
452 reg [15:0] memory [0:255];
453
454 initial begin
455 if (INIT_FILE != "")
456 $readmemh(INIT_FILE, memory);
457 else
458 for (i=0; i<16; i=i+1) begin
459 memory[ 0*16 + i] = INIT_0[16*i +: 16];
460 memory[ 1*16 + i] = INIT_1[16*i +: 16];
461 memory[ 2*16 + i] = INIT_2[16*i +: 16];
462 memory[ 3*16 + i] = INIT_3[16*i +: 16];
463 memory[ 4*16 + i] = INIT_4[16*i +: 16];
464 memory[ 5*16 + i] = INIT_5[16*i +: 16];
465 memory[ 6*16 + i] = INIT_6[16*i +: 16];
466 memory[ 7*16 + i] = INIT_7[16*i +: 16];
467 memory[ 8*16 + i] = INIT_8[16*i +: 16];
468 memory[ 9*16 + i] = INIT_9[16*i +: 16];
469 memory[10*16 + i] = INIT_A[16*i +: 16];
470 memory[11*16 + i] = INIT_B[16*i +: 16];
471 memory[12*16 + i] = INIT_C[16*i +: 16];
472 memory[13*16 + i] = INIT_D[16*i +: 16];
473 memory[14*16 + i] = INIT_E[16*i +: 16];
474 memory[15*16 + i] = INIT_F[16*i +: 16];
475 end
476 end
477
478 always @(posedge WCLK) begin
479 if (WE && WCLKE) begin
480 if (!WMASK_I[ 0]) memory[WADDR[7:0]][ 0] <= WDATA_I[ 0];
481 if (!WMASK_I[ 1]) memory[WADDR[7:0]][ 1] <= WDATA_I[ 1];
482 if (!WMASK_I[ 2]) memory[WADDR[7:0]][ 2] <= WDATA_I[ 2];
483 if (!WMASK_I[ 3]) memory[WADDR[7:0]][ 3] <= WDATA_I[ 3];
484 if (!WMASK_I[ 4]) memory[WADDR[7:0]][ 4] <= WDATA_I[ 4];
485 if (!WMASK_I[ 5]) memory[WADDR[7:0]][ 5] <= WDATA_I[ 5];
486 if (!WMASK_I[ 6]) memory[WADDR[7:0]][ 6] <= WDATA_I[ 6];
487 if (!WMASK_I[ 7]) memory[WADDR[7:0]][ 7] <= WDATA_I[ 7];
488 if (!WMASK_I[ 8]) memory[WADDR[7:0]][ 8] <= WDATA_I[ 8];
489 if (!WMASK_I[ 9]) memory[WADDR[7:0]][ 9] <= WDATA_I[ 9];
490 if (!WMASK_I[10]) memory[WADDR[7:0]][10] <= WDATA_I[10];
491 if (!WMASK_I[11]) memory[WADDR[7:0]][11] <= WDATA_I[11];
492 if (!WMASK_I[12]) memory[WADDR[7:0]][12] <= WDATA_I[12];
493 if (!WMASK_I[13]) memory[WADDR[7:0]][13] <= WDATA_I[13];
494 if (!WMASK_I[14]) memory[WADDR[7:0]][14] <= WDATA_I[14];
495 if (!WMASK_I[15]) memory[WADDR[7:0]][15] <= WDATA_I[15];
496 end
497 end
498
499 always @(posedge RCLK) begin
500 if (RE && RCLKE) begin
501 RDATA_I <= memory[RADDR[7:0]] & ~RMASK_I;
502 end
503 end
504 `endif
505 endmodule
506
507 module SB_RAM40_4KNR (
508 output [15:0] RDATA,
509 input RCLKN, RCLKE, RE,
510 input [10:0] RADDR,
511 input WCLK, WCLKE, WE,
512 input [10:0] WADDR,
513 input [15:0] MASK, WDATA
514 );
515 parameter WRITE_MODE = 0;
516 parameter READ_MODE = 0;
517
518 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
519 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
520 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
521 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
522 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
523 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
524 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
525 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
526 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
527 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
528 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
529 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
530 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
531 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
532 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
533 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
534
535 parameter INIT_FILE = "";
536
537 SB_RAM40_4K #(
538 .WRITE_MODE(WRITE_MODE),
539 .READ_MODE (READ_MODE ),
540 .INIT_0 (INIT_0 ),
541 .INIT_1 (INIT_1 ),
542 .INIT_2 (INIT_2 ),
543 .INIT_3 (INIT_3 ),
544 .INIT_4 (INIT_4 ),
545 .INIT_5 (INIT_5 ),
546 .INIT_6 (INIT_6 ),
547 .INIT_7 (INIT_7 ),
548 .INIT_8 (INIT_8 ),
549 .INIT_9 (INIT_9 ),
550 .INIT_A (INIT_A ),
551 .INIT_B (INIT_B ),
552 .INIT_C (INIT_C ),
553 .INIT_D (INIT_D ),
554 .INIT_E (INIT_E ),
555 .INIT_F (INIT_F ),
556 .INIT_FILE (INIT_FILE )
557 ) RAM (
558 .RDATA(RDATA),
559 .RCLK (~RCLKN),
560 .RCLKE(RCLKE),
561 .RE (RE ),
562 .RADDR(RADDR),
563 .WCLK (WCLK ),
564 .WCLKE(WCLKE),
565 .WE (WE ),
566 .WADDR(WADDR),
567 .MASK (MASK ),
568 .WDATA(WDATA)
569 );
570 endmodule
571
572 module SB_RAM40_4KNW (
573 output [15:0] RDATA,
574 input RCLK, RCLKE, RE,
575 input [10:0] RADDR,
576 input WCLKN, WCLKE, WE,
577 input [10:0] WADDR,
578 input [15:0] MASK, WDATA
579 );
580 parameter WRITE_MODE = 0;
581 parameter READ_MODE = 0;
582
583 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
584 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
585 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
586 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
587 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
588 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
589 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
590 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
591 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
592 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
593 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
594 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
595 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
596 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
597 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
598 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
599
600 parameter INIT_FILE = "";
601
602 SB_RAM40_4K #(
603 .WRITE_MODE(WRITE_MODE),
604 .READ_MODE (READ_MODE ),
605 .INIT_0 (INIT_0 ),
606 .INIT_1 (INIT_1 ),
607 .INIT_2 (INIT_2 ),
608 .INIT_3 (INIT_3 ),
609 .INIT_4 (INIT_4 ),
610 .INIT_5 (INIT_5 ),
611 .INIT_6 (INIT_6 ),
612 .INIT_7 (INIT_7 ),
613 .INIT_8 (INIT_8 ),
614 .INIT_9 (INIT_9 ),
615 .INIT_A (INIT_A ),
616 .INIT_B (INIT_B ),
617 .INIT_C (INIT_C ),
618 .INIT_D (INIT_D ),
619 .INIT_E (INIT_E ),
620 .INIT_F (INIT_F ),
621 .INIT_FILE (INIT_FILE )
622 ) RAM (
623 .RDATA(RDATA),
624 .RCLK (RCLK ),
625 .RCLKE(RCLKE),
626 .RE (RE ),
627 .RADDR(RADDR),
628 .WCLK (~WCLKN),
629 .WCLKE(WCLKE),
630 .WE (WE ),
631 .WADDR(WADDR),
632 .MASK (MASK ),
633 .WDATA(WDATA)
634 );
635 endmodule
636
637 module SB_RAM40_4KNRNW (
638 output [15:0] RDATA,
639 input RCLKN, RCLKE, RE,
640 input [10:0] RADDR,
641 input WCLKN, WCLKE, WE,
642 input [10:0] WADDR,
643 input [15:0] MASK, WDATA
644 );
645 parameter WRITE_MODE = 0;
646 parameter READ_MODE = 0;
647
648 parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
649 parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
650 parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
651 parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
652 parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
653 parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
654 parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
655 parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
656 parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
657 parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
658 parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
659 parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
660 parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
661 parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
662 parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
663 parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
664
665 parameter INIT_FILE = "";
666
667 SB_RAM40_4K #(
668 .WRITE_MODE(WRITE_MODE),
669 .READ_MODE (READ_MODE ),
670 .INIT_0 (INIT_0 ),
671 .INIT_1 (INIT_1 ),
672 .INIT_2 (INIT_2 ),
673 .INIT_3 (INIT_3 ),
674 .INIT_4 (INIT_4 ),
675 .INIT_5 (INIT_5 ),
676 .INIT_6 (INIT_6 ),
677 .INIT_7 (INIT_7 ),
678 .INIT_8 (INIT_8 ),
679 .INIT_9 (INIT_9 ),
680 .INIT_A (INIT_A ),
681 .INIT_B (INIT_B ),
682 .INIT_C (INIT_C ),
683 .INIT_D (INIT_D ),
684 .INIT_E (INIT_E ),
685 .INIT_F (INIT_F ),
686 .INIT_FILE (INIT_FILE )
687 ) RAM (
688 .RDATA(RDATA),
689 .RCLK (~RCLKN),
690 .RCLKE(RCLKE),
691 .RE (RE ),
692 .RADDR(RADDR),
693 .WCLK (~WCLKN),
694 .WCLKE(WCLKE),
695 .WE (WE ),
696 .WADDR(WADDR),
697 .MASK (MASK ),
698 .WDATA(WDATA)
699 );
700 endmodule
701
702 // Packed IceStorm Logic Cells
703
704 module ICESTORM_LC (
705 input I0, I1, I2, I3, CIN, CLK, CEN, SR,
706 output LO, O, COUT
707 );
708 parameter [15:0] LUT_INIT = 0;
709
710 parameter [0:0] NEG_CLK = 0;
711 parameter [0:0] CARRY_ENABLE = 0;
712 parameter [0:0] DFF_ENABLE = 0;
713 parameter [0:0] SET_NORESET = 0;
714 parameter [0:0] ASYNC_SR = 0;
715
716 parameter [0:0] CIN_CONST = 0;
717 parameter [0:0] CIN_SET = 0;
718
719 wire mux_cin = CIN_CONST ? CIN_SET : CIN;
720
721 assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && mux_cin) : 1'bx;
722
723 wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
724 wire [3:0] lut_s2 = I2 ? lut_s3[ 7:4] : lut_s3[3:0];
725 wire [1:0] lut_s1 = I1 ? lut_s2[ 3:2] : lut_s2[1:0];
726 wire lut_o = I0 ? lut_s1[ 1] : lut_s1[ 0];
727
728 assign LO = lut_o;
729
730 wire polarized_clk;
731 assign polarized_clk = CLK ^ NEG_CLK;
732
733 reg o_reg;
734 always @(posedge polarized_clk)
735 if (CEN)
736 o_reg <= SR ? SET_NORESET : lut_o;
737
738 reg o_reg_async;
739 always @(posedge polarized_clk, posedge SR)
740 if (SR)
741 o_reg <= SET_NORESET;
742 else if (CEN)
743 o_reg <= lut_o;
744
745 assign O = DFF_ENABLE ? ASYNC_SR ? o_reg_async : o_reg : lut_o;
746 endmodule
747
748 // SiliconBlue PLL Cells
749
750 (* blackbox *)
751 module SB_PLL40_CORE (
752 input REFERENCECLK,
753 output PLLOUTCORE,
754 output PLLOUTGLOBAL,
755 input EXTFEEDBACK,
756 input [7:0] DYNAMICDELAY,
757 output LOCK,
758 input BYPASS,
759 input RESETB,
760 input LATCHINPUTVALUE,
761 output SDO,
762 input SDI,
763 input SCLK
764 );
765 parameter FEEDBACK_PATH = "SIMPLE";
766 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
767 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
768 parameter SHIFTREG_DIV_MODE = 1'b0;
769 parameter FDA_FEEDBACK = 4'b0000;
770 parameter FDA_RELATIVE = 4'b0000;
771 parameter PLLOUT_SELECT = "GENCLK";
772 parameter DIVR = 4'b0000;
773 parameter DIVF = 7'b0000000;
774 parameter DIVQ = 3'b000;
775 parameter FILTER_RANGE = 3'b000;
776 parameter ENABLE_ICEGATE = 1'b0;
777 parameter TEST_MODE = 1'b0;
778 parameter EXTERNAL_DIVIDE_FACTOR = 1;
779 endmodule
780
781 (* blackbox *)
782 module SB_PLL40_PAD (
783 input PACKAGEPIN,
784 output PLLOUTCORE,
785 output PLLOUTGLOBAL,
786 input EXTFEEDBACK,
787 input [7:0] DYNAMICDELAY,
788 output LOCK,
789 input BYPASS,
790 input RESETB,
791 input LATCHINPUTVALUE,
792 output SDO,
793 input SDI,
794 input SCLK
795 );
796 parameter FEEDBACK_PATH = "SIMPLE";
797 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
798 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
799 parameter SHIFTREG_DIV_MODE = 1'b0;
800 parameter FDA_FEEDBACK = 4'b0000;
801 parameter FDA_RELATIVE = 4'b0000;
802 parameter PLLOUT_SELECT = "GENCLK";
803 parameter DIVR = 4'b0000;
804 parameter DIVF = 7'b0000000;
805 parameter DIVQ = 3'b000;
806 parameter FILTER_RANGE = 3'b000;
807 parameter ENABLE_ICEGATE = 1'b0;
808 parameter TEST_MODE = 1'b0;
809 parameter EXTERNAL_DIVIDE_FACTOR = 1;
810 endmodule
811
812 (* blackbox *)
813 module SB_PLL40_2_PAD (
814 input PACKAGEPIN,
815 output PLLOUTCOREA,
816 output PLLOUTGLOBALA,
817 output PLLOUTCOREB,
818 output PLLOUTGLOBALB,
819 input EXTFEEDBACK,
820 input [7:0] DYNAMICDELAY,
821 output LOCK,
822 input BYPASS,
823 input RESETB,
824 input LATCHINPUTVALUE,
825 output SDO,
826 input SDI,
827 input SCLK
828 );
829 parameter FEEDBACK_PATH = "SIMPLE";
830 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
831 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
832 parameter SHIFTREG_DIV_MODE = 1'b0;
833 parameter FDA_FEEDBACK = 4'b0000;
834 parameter FDA_RELATIVE = 4'b0000;
835 parameter PLLOUT_SELECT_PORTB = "GENCLK";
836 parameter DIVR = 4'b0000;
837 parameter DIVF = 7'b0000000;
838 parameter DIVQ = 3'b000;
839 parameter FILTER_RANGE = 3'b000;
840 parameter ENABLE_ICEGATE_PORTA = 1'b0;
841 parameter ENABLE_ICEGATE_PORTB = 1'b0;
842 parameter TEST_MODE = 1'b0;
843 parameter EXTERNAL_DIVIDE_FACTOR = 1;
844 endmodule
845
846 (* blackbox *)
847 module SB_PLL40_2F_CORE (
848 input REFERENCECLK,
849 output PLLOUTCOREA,
850 output PLLOUTGLOBALA,
851 output PLLOUTCOREB,
852 output PLLOUTGLOBALB,
853 input EXTFEEDBACK,
854 input [7:0] DYNAMICDELAY,
855 output LOCK,
856 input BYPASS,
857 input RESETB,
858 input LATCHINPUTVALUE,
859 output SDO,
860 input SDI,
861 input SCLK
862 );
863 parameter FEEDBACK_PATH = "SIMPLE";
864 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
865 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
866 parameter SHIFTREG_DIV_MODE = 1'b0;
867 parameter FDA_FEEDBACK = 4'b0000;
868 parameter FDA_RELATIVE = 4'b0000;
869 parameter PLLOUT_SELECT_PORTA = "GENCLK";
870 parameter PLLOUT_SELECT_PORTB = "GENCLK";
871 parameter DIVR = 4'b0000;
872 parameter DIVF = 7'b0000000;
873 parameter DIVQ = 3'b000;
874 parameter FILTER_RANGE = 3'b000;
875 parameter ENABLE_ICEGATE_PORTA = 1'b0;
876 parameter ENABLE_ICEGATE_PORTB = 1'b0;
877 parameter TEST_MODE = 1'b0;
878 parameter EXTERNAL_DIVIDE_FACTOR = 1;
879 endmodule
880
881 (* blackbox *)
882 module SB_PLL40_2F_PAD (
883 input PACKAGEPIN,
884 output PLLOUTCOREA,
885 output PLLOUTGLOBALA,
886 output PLLOUTCOREB,
887 output PLLOUTGLOBALB,
888 input EXTFEEDBACK,
889 input [7:0] DYNAMICDELAY,
890 output LOCK,
891 input BYPASS,
892 input RESETB,
893 input LATCHINPUTVALUE,
894 output SDO,
895 input SDI,
896 input SCLK
897 );
898 parameter FEEDBACK_PATH = "SIMPLE";
899 parameter DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
900 parameter DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
901 parameter SHIFTREG_DIV_MODE = 2'b00;
902 parameter FDA_FEEDBACK = 4'b0000;
903 parameter FDA_RELATIVE = 4'b0000;
904 parameter PLLOUT_SELECT_PORTA = "GENCLK";
905 parameter PLLOUT_SELECT_PORTB = "GENCLK";
906 parameter DIVR = 4'b0000;
907 parameter DIVF = 7'b0000000;
908 parameter DIVQ = 3'b000;
909 parameter FILTER_RANGE = 3'b000;
910 parameter ENABLE_ICEGATE_PORTA = 1'b0;
911 parameter ENABLE_ICEGATE_PORTB = 1'b0;
912 parameter TEST_MODE = 1'b0;
913 parameter EXTERNAL_DIVIDE_FACTOR = 1;
914 endmodule
915
916 // SiliconBlue Device Configuration Cells
917
918 (* blackbox, keep *)
919 module SB_WARMBOOT (
920 input BOOT,
921 input S1,
922 input S0
923 );
924 endmodule
925
926 module SB_SPRAM256KA (
927 input [13:0] ADDRESS,
928 input [15:0] DATAIN,
929 input [3:0] MASKWREN,
930 input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
931 output reg [15:0] DATAOUT
932 );
933 `ifndef BLACKBOX
934 `ifndef EQUIV
935 reg [15:0] mem [0:16383];
936 wire off = SLEEP || !POWEROFF;
937 integer i;
938
939 always @(negedge POWEROFF) begin
940 for (i = 0; i <= 16383; i = i+1)
941 mem[i] = 'bx;
942 end
943
944 always @(posedge CLOCK, posedge off) begin
945 if (off) begin
946 DATAOUT <= 0;
947 end else
948 if (CHIPSELECT && !STANDBY && !WREN) begin
949 DATAOUT <= mem[ADDRESS];
950 end else begin
951 if (CHIPSELECT && !STANDBY && WREN) begin
952 if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0];
953 if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4];
954 if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8];
955 if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12];
956 end
957 DATAOUT <= 'bx;
958 end
959 end
960 `endif
961 `endif
962 endmodule
963
964 (* blackbox *)
965 module SB_HFOSC(
966 input TRIM0,
967 input TRIM1,
968 input TRIM2,
969 input TRIM3,
970 input TRIM4,
971 input TRIM5,
972 input TRIM6,
973 input TRIM7,
974 input TRIM8,
975 input TRIM9,
976 input CLKHFPU,
977 input CLKHFEN,
978 output CLKHF
979 );
980 parameter TRIM_EN = "0b0";
981 parameter CLKHF_DIV = "0b00";
982 endmodule
983
984 (* blackbox *)
985 module SB_LFOSC(
986 input CLKLFPU,
987 input CLKLFEN,
988 output CLKLF
989 );
990 endmodule
991
992 (* blackbox *)
993 module SB_RGBA_DRV(
994 input CURREN,
995 input RGBLEDEN,
996 input RGB0PWM,
997 input RGB1PWM,
998 input RGB2PWM,
999 output RGB0,
1000 output RGB1,
1001 output RGB2
1002 );
1003 parameter CURRENT_MODE = "0b0";
1004 parameter RGB0_CURRENT = "0b000000";
1005 parameter RGB1_CURRENT = "0b000000";
1006 parameter RGB2_CURRENT = "0b000000";
1007 endmodule
1008
1009 (* blackbox *)
1010 module SB_LED_DRV_CUR(
1011 input EN,
1012 output LEDPU
1013 );
1014 endmodule
1015
1016 (* blackbox *)
1017 module SB_RGB_DRV(
1018 input RGBLEDEN,
1019 input RGB0PWM,
1020 input RGB1PWM,
1021 input RGB2PWM,
1022 input RGBPU,
1023 output RGB0,
1024 output RGB1,
1025 output RGB2
1026 );
1027 parameter CURRENT_MODE = "0b0";
1028 parameter RGB0_CURRENT = "0b000000";
1029 parameter RGB1_CURRENT = "0b000000";
1030 parameter RGB2_CURRENT = "0b000000";
1031 endmodule
1032
1033 (* blackbox *)
1034 module SB_I2C(
1035 input SBCLKI,
1036 input SBRWI,
1037 input SBSTBI,
1038 input SBADRI7,
1039 input SBADRI6,
1040 input SBADRI5,
1041 input SBADRI4,
1042 input SBADRI3,
1043 input SBADRI2,
1044 input SBADRI1,
1045 input SBADRI0,
1046 input SBDATI7,
1047 input SBDATI6,
1048 input SBDATI5,
1049 input SBDATI4,
1050 input SBDATI3,
1051 input SBDATI2,
1052 input SBDATI1,
1053 input SBDATI0,
1054 input SCLI,
1055 input SDAI,
1056 output SBDATO7,
1057 output SBDATO6,
1058 output SBDATO5,
1059 output SBDATO4,
1060 output SBDATO3,
1061 output SBDATO2,
1062 output SBDATO1,
1063 output SBDATO0,
1064 output SBACKO,
1065 output I2CIRQ,
1066 output I2CWKUP,
1067 output SCLO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
1068 output SCLOE,
1069 output SDAO,
1070 output SDAOE
1071 );
1072 parameter I2C_SLAVE_INIT_ADDR = "0b1111100001";
1073 parameter BUS_ADDR74 = "0b0001";
1074 endmodule
1075
1076 (* blackbox *)
1077 module SB_SPI (
1078 input SBCLKI,
1079 input SBRWI,
1080 input SBSTBI,
1081 input SBADRI7,
1082 input SBADRI6,
1083 input SBADRI5,
1084 input SBADRI4,
1085 input SBADRI3,
1086 input SBADRI2,
1087 input SBADRI1,
1088 input SBADRI0,
1089 input SBDATI7,
1090 input SBDATI6,
1091 input SBDATI5,
1092 input SBDATI4,
1093 input SBDATI3,
1094 input SBDATI2,
1095 input SBDATI1,
1096 input SBDATI0,
1097 input MI,
1098 input SI,
1099 input SCKI,
1100 input SCSNI,
1101 output SBDATO7,
1102 output SBDATO6,
1103 output SBDATO5,
1104 output SBDATO4,
1105 output SBDATO3,
1106 output SBDATO2,
1107 output SBDATO1,
1108 output SBDATO0,
1109 output SBACKO,
1110 output SPIIRQ,
1111 output SPIWKUP,
1112 output SO,
1113 output SOE,
1114 output MO,
1115 output MOE,
1116 output SCKO, //inout in the SB verilog library, but output in the VHDL and PDF libs and seemingly in the HW itself
1117 output SCKOE,
1118 output MCSNO3,
1119 output MCSNO2,
1120 output MCSNO1,
1121 output MCSNO0,
1122 output MCSNOE3,
1123 output MCSNOE2,
1124 output MCSNOE1,
1125 output MCSNOE0
1126 );
1127 parameter BUS_ADDR74 = "0b0000";
1128 endmodule
1129
1130 (* blackbox *)
1131 module SB_LEDDA_IP(
1132 input LEDDCS,
1133 input LEDDCLK,
1134 input LEDDDAT7,
1135 input LEDDDAT6,
1136 input LEDDDAT5,
1137 input LEDDDAT4,
1138 input LEDDDAT3,
1139 input LEDDDAT2,
1140 input LEDDDAT1,
1141 input LEDDDAT0,
1142 input LEDDADDR3,
1143 input LEDDADDR2,
1144 input LEDDADDR1,
1145 input LEDDADDR0,
1146 input LEDDDEN,
1147 input LEDDEXE,
1148 input LEDDRST,
1149 output PWMOUT0,
1150 output PWMOUT1,
1151 output PWMOUT2,
1152 output LEDDON
1153 );
1154 endmodule
1155
1156 (* blackbox *)
1157 module SB_FILTER_50NS(
1158 input FILTERIN,
1159 output FILTEROUT
1160 );
1161 endmodule
1162
1163 module SB_IO_I3C (
1164 inout PACKAGE_PIN,
1165 input LATCH_INPUT_VALUE,
1166 input CLOCK_ENABLE,
1167 input INPUT_CLK,
1168 input OUTPUT_CLK,
1169 input OUTPUT_ENABLE,
1170 input D_OUT_0,
1171 input D_OUT_1,
1172 output D_IN_0,
1173 output D_IN_1,
1174 input PU_ENB,
1175 input WEAK_PU_ENB
1176 );
1177 parameter [5:0] PIN_TYPE = 6'b000000;
1178 parameter [0:0] PULLUP = 1'b0;
1179 parameter [0:0] WEAK_PULLUP = 1'b0;
1180 parameter [0:0] NEG_TRIGGER = 1'b0;
1181 parameter IO_STANDARD = "SB_LVCMOS";
1182
1183 `ifndef BLACKBOX
1184 reg dout, din_0, din_1;
1185 reg din_q_0, din_q_1;
1186 reg dout_q_0, dout_q_1;
1187 reg outena_q;
1188
1189 generate if (!NEG_TRIGGER) begin
1190 always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
1191 always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
1192 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
1193 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
1194 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
1195 end else begin
1196 always @(negedge INPUT_CLK) if (CLOCK_ENABLE) din_q_0 <= PACKAGE_PIN;
1197 always @(posedge INPUT_CLK) if (CLOCK_ENABLE) din_q_1 <= PACKAGE_PIN;
1198 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_0 <= D_OUT_0;
1199 always @(posedge OUTPUT_CLK) if (CLOCK_ENABLE) dout_q_1 <= D_OUT_1;
1200 always @(negedge OUTPUT_CLK) if (CLOCK_ENABLE) outena_q <= OUTPUT_ENABLE;
1201 end endgenerate
1202
1203 always @* begin
1204 if (!PIN_TYPE[1] || !LATCH_INPUT_VALUE)
1205 din_0 = PIN_TYPE[0] ? PACKAGE_PIN : din_q_0;
1206 din_1 = din_q_1;
1207 end
1208
1209 // work around simulation glitches on dout in DDR mode
1210 reg outclk_delayed_1;
1211 reg outclk_delayed_2;
1212 always @* outclk_delayed_1 <= OUTPUT_CLK;
1213 always @* outclk_delayed_2 <= outclk_delayed_1;
1214
1215 always @* begin
1216 if (PIN_TYPE[3])
1217 dout = PIN_TYPE[2] ? !dout_q_0 : D_OUT_0;
1218 else
1219 dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
1220 end
1221
1222 assign D_IN_0 = din_0, D_IN_1 = din_1;
1223
1224 generate
1225 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGE_PIN = dout;
1226 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGE_PIN = OUTPUT_ENABLE ? dout : 1'bz;
1227 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz;
1228 endgenerate
1229 `endif
1230 endmodule
1231
1232 module SB_IO_OD (
1233 inout PACKAGEPIN,
1234 input LATCHINPUTVALUE,
1235 input CLOCKENABLE,
1236 input INPUTCLK,
1237 input OUTPUTCLK,
1238 input OUTPUTENABLE,
1239 input DOUT1,
1240 input DOUT0,
1241 output DIN1,
1242 output DIN0
1243 );
1244 parameter [5:0] PIN_TYPE = 6'b000000;
1245 parameter [0:0] NEG_TRIGGER = 1'b0;
1246
1247 `ifndef BLACKBOX
1248 reg dout, din_0, din_1;
1249 reg din_q_0, din_q_1;
1250 reg dout_q_0, dout_q_1;
1251 reg outena_q;
1252
1253 generate if (!NEG_TRIGGER) begin
1254 always @(posedge INPUTCLK) if (CLOCKENABLE) din_q_0 <= PACKAGEPIN;
1255 always @(negedge INPUTCLK) if (CLOCKENABLE) din_q_1 <= PACKAGEPIN;
1256 always @(posedge OUTPUTCLK) if (CLOCKENABLE) dout_q_0 <= DOUT0;
1257 always @(negedge OUTPUTCLK) if (CLOCKENABLE) dout_q_1 <= DOUT1;
1258 always @(posedge OUTPUTCLK) if (CLOCKENABLE) outena_q <= OUTPUTENABLE;
1259 end else begin
1260 always @(negedge INPUTCLK) if (CLOCKENABLE) din_q_0 <= PACKAGEPIN;
1261 always @(posedge INPUTCLK) if (CLOCKENABLE) din_q_1 <= PACKAGEPIN;
1262 always @(negedge OUTPUTCLK) if (CLOCKENABLE) dout_q_0 <= DOUT0;
1263 always @(posedge OUTPUTCLK) if (CLOCKENABLE) dout_q_1 <= DOUT1;
1264 always @(negedge OUTPUTCLK) if (CLOCKENABLE) outena_q <= OUTPUTENABLE;
1265 end endgenerate
1266
1267 always @* begin
1268 if (!PIN_TYPE[1] || !LATCHINPUTVALUE)
1269 din_0 = PIN_TYPE[0] ? PACKAGEPIN : din_q_0;
1270 din_1 = din_q_1;
1271 end
1272
1273 // work around simulation glitches on dout in DDR mode
1274 reg outclk_delayed_1;
1275 reg outclk_delayed_2;
1276 always @* outclk_delayed_1 <= OUTPUTCLK;
1277 always @* outclk_delayed_2 <= outclk_delayed_1;
1278
1279 always @* begin
1280 if (PIN_TYPE[3])
1281 dout = PIN_TYPE[2] ? !dout_q_0 : DOUT0;
1282 else
1283 dout = (outclk_delayed_2 ^ NEG_TRIGGER) || PIN_TYPE[2] ? dout_q_0 : dout_q_1;
1284 end
1285
1286 assign DIN0 = din_0, DIN1 = din_1;
1287
1288 generate
1289 if (PIN_TYPE[5:4] == 2'b01) assign PACKAGEPIN = dout ? 1'bz : 1'b0;
1290 if (PIN_TYPE[5:4] == 2'b10) assign PACKAGEPIN = OUTPUTENABLE ? (dout ? 1'bz : 1'b0) : 1'bz;
1291 if (PIN_TYPE[5:4] == 2'b11) assign PACKAGEPIN = outena_q ? (dout ? 1'bz : 1'b0) : 1'bz;
1292 endgenerate
1293 `endif
1294 endmodule
1295
1296 module SB_MAC16 (
1297 input CLK, CE,
1298 input [15:0] C, A, B, D,
1299 input AHOLD, BHOLD, CHOLD, DHOLD,
1300 input IRSTTOP, IRSTBOT,
1301 input ORSTTOP, ORSTBOT,
1302 input OLOADTOP, OLOADBOT,
1303 input ADDSUBTOP, ADDSUBBOT,
1304 input OHOLDTOP, OHOLDBOT,
1305 input CI, ACCUMCI, SIGNEXTIN,
1306 output [31:0] O,
1307 output CO, ACCUMCO, SIGNEXTOUT
1308 );
1309 parameter [0:0] NEG_TRIGGER = 0;
1310 parameter [0:0] C_REG = 0;
1311 parameter [0:0] A_REG = 0;
1312 parameter [0:0] B_REG = 0;
1313 parameter [0:0] D_REG = 0;
1314 parameter [0:0] TOP_8x8_MULT_REG = 0;
1315 parameter [0:0] BOT_8x8_MULT_REG = 0;
1316 parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
1317 parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
1318 parameter [1:0] TOPOUTPUT_SELECT = 0;
1319 parameter [1:0] TOPADDSUB_LOWERINPUT = 0;
1320 parameter [0:0] TOPADDSUB_UPPERINPUT = 0;
1321 parameter [1:0] TOPADDSUB_CARRYSELECT = 0;
1322 parameter [1:0] BOTOUTPUT_SELECT = 0;
1323 parameter [1:0] BOTADDSUB_LOWERINPUT = 0;
1324 parameter [0:0] BOTADDSUB_UPPERINPUT = 0;
1325 parameter [1:0] BOTADDSUB_CARRYSELECT = 0;
1326 parameter [0:0] MODE_8x8 = 0;
1327 parameter [0:0] A_SIGNED = 0;
1328 parameter [0:0] B_SIGNED = 0;
1329
1330 wire clock = CLK ^ NEG_TRIGGER;
1331
1332 // internal wires, compare Figure on page 133 of ICE Technology Library 3.0 and Fig 2 on page 2 of Lattice TN1295-DSP
1333 // http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201608.pdf
1334 // https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/AD/DSPFunctionUsageGuideforICE40Devices.ashx
1335 wire [15:0] iA, iB, iC, iD;
1336 wire [15:0] iF, iJ, iK, iG;
1337 wire [31:0] iL, iH;
1338 wire [15:0] iW, iX, iP, iQ;
1339 wire [15:0] iY, iZ, iR, iS;
1340 wire HCI, LCI, LCO;
1341
1342 // Regs C and A
1343 reg [15:0] rC, rA;
1344 always @(posedge clock, posedge IRSTTOP) begin
1345 if (IRSTTOP) begin
1346 rC <= 0;
1347 rA <= 0;
1348 end else if (CE) begin
1349 if (!CHOLD) rC <= C;
1350 if (!AHOLD) rA <= A;
1351 end
1352 end
1353 assign iC = C_REG ? rC : C;
1354 assign iA = A_REG ? rA : A;
1355
1356 // Regs B and D
1357 reg [15:0] rB, rD;
1358 always @(posedge clock, posedge IRSTBOT) begin
1359 if (IRSTBOT) begin
1360 rB <= 0;
1361 rD <= 0;
1362 end else if (CE) begin
1363 if (!BHOLD) rB <= B;
1364 if (!DHOLD) rD <= D;
1365 end
1366 end
1367 assign iB = B_REG ? rB : B;
1368 assign iD = D_REG ? rD : D;
1369
1370 // Multiplier Stage
1371 wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
1372 wire [15:0] Ah, Al, Bh, Bl;
1373 assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]};
1374 assign Al = {A_SIGNED && MODE_8x8 ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
1375 assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]};
1376 assign Bl = {B_SIGNED && MODE_8x8 ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
1377 assign p_Ah_Bh = Ah * Bh; // F
1378 assign p_Al_Bh = {8'b0, Al[7:0]} * Bh; // J
1379 assign p_Ah_Bl = Ah * {8'b0, Bl[7:0]}; // K
1380 assign p_Al_Bl = Al * Bl; // G
1381
1382 // Regs F and J
1383 reg [15:0] rF, rJ;
1384 always @(posedge clock, posedge IRSTTOP) begin
1385 if (IRSTTOP) begin
1386 rF <= 0;
1387 rJ <= 0;
1388 end else if (CE) begin
1389 rF <= p_Ah_Bh;
1390 if (!MODE_8x8) rJ <= p_Al_Bh;
1391 end
1392 end
1393 assign iF = TOP_8x8_MULT_REG ? rF : p_Ah_Bh;
1394 assign iJ = PIPELINE_16x16_MULT_REG1 ? rJ : p_Al_Bh;
1395
1396 // Regs K and G
1397 reg [15:0] rK, rG;
1398 always @(posedge clock, posedge IRSTBOT) begin
1399 if (IRSTBOT) begin
1400 rK <= 0;
1401 rG <= 0;
1402 end else if (CE) begin
1403 if (!MODE_8x8) rK <= p_Ah_Bl;
1404 rG <= p_Al_Bl;
1405 end
1406 end
1407 assign iK = PIPELINE_16x16_MULT_REG1 ? rK : p_Ah_Bl;
1408 assign iG = BOT_8x8_MULT_REG ? rG : p_Al_Bl;
1409
1410 // Adder Stage
1411 wire [23:0] iK_e = {A_SIGNED ? {8{iK[15]}} : 8'b0, iK};
1412 wire [23:0] iJ_e = {B_SIGNED ? {8{iJ[15]}} : 8'b0, iJ};
1413 assign iL = iG + (iK_e << 8) + (iJ_e << 8) + (iF << 16);
1414
1415 // Reg H
1416 reg [31:0] rH;
1417 always @(posedge clock, posedge IRSTBOT) begin
1418 if (IRSTBOT) begin
1419 rH <= 0;
1420 end else if (CE) begin
1421 if (!MODE_8x8) rH <= iL;
1422 end
1423 end
1424 assign iH = PIPELINE_16x16_MULT_REG2 ? rH : iL;
1425
1426 // Hi Output Stage
1427 wire [15:0] XW, Oh;
1428 reg [15:0] rQ;
1429 assign iW = TOPADDSUB_UPPERINPUT ? iC : iQ;
1430 assign iX = (TOPADDSUB_LOWERINPUT == 0) ? iA : (TOPADDSUB_LOWERINPUT == 1) ? iF : (TOPADDSUB_LOWERINPUT == 2) ? iH[31:16] : {16{iZ[15]}};
1431 assign {ACCUMCO, XW} = iX + (iW ^ {16{ADDSUBTOP}}) + HCI;
1432 assign CO = ACCUMCO ^ ADDSUBTOP;
1433 assign iP = OLOADTOP ? iC : XW ^ {16{ADDSUBTOP}};
1434 always @(posedge clock, posedge ORSTTOP) begin
1435 if (ORSTTOP) begin
1436 rQ <= 0;
1437 end else if (CE) begin
1438 if (!OHOLDTOP) rQ <= iP;
1439 end
1440 end
1441 assign iQ = rQ;
1442 assign Oh = (TOPOUTPUT_SELECT == 0) ? iP : (TOPOUTPUT_SELECT == 1) ? iQ : (TOPOUTPUT_SELECT == 2) ? iF : iH[31:16];
1443 assign HCI = (TOPADDSUB_CARRYSELECT == 0) ? 1'b0 : (TOPADDSUB_CARRYSELECT == 1) ? 1'b1 : (TOPADDSUB_CARRYSELECT == 2) ? LCO : LCO ^ ADDSUBBOT;
1444 assign SIGNEXTOUT = iX[15];
1445
1446 // Lo Output Stage
1447 wire [15:0] YZ, Ol;
1448 reg [15:0] rS;
1449 assign iY = BOTADDSUB_UPPERINPUT ? iD : iS;
1450 assign iZ = (BOTADDSUB_LOWERINPUT == 0) ? iB : (BOTADDSUB_LOWERINPUT == 1) ? iG : (BOTADDSUB_LOWERINPUT == 2) ? iH[15:0] : {16{SIGNEXTIN}};
1451 assign {LCO, YZ} = iZ + (iY ^ {16{ADDSUBBOT}}) + LCI;
1452 assign iR = OLOADBOT ? iD : YZ ^ {16{ADDSUBBOT}};
1453 always @(posedge clock, posedge ORSTBOT) begin
1454 if (ORSTBOT) begin
1455 rS <= 0;
1456 end else if (CE) begin
1457 if (!OHOLDBOT) rS <= iR;
1458 end
1459 end
1460 assign iS = rS;
1461 assign Ol = (BOTOUTPUT_SELECT == 0) ? iR : (BOTOUTPUT_SELECT == 1) ? iS : (BOTOUTPUT_SELECT == 2) ? iG : iH[15:0];
1462 assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI;
1463 assign O = {Oh, Ol};
1464 endmodule