techlibs/ice40/ice40_ffssr.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/yosys.h"
  21 #include "kernel/sigtools.h"
  22
  23 USING_YOSYS_NAMESPACE
  24 PRIVATE_NAMESPACE_BEGIN
  25
  26 struct Ice40FfssrPass : public Pass {
  27         Ice40FfssrPass() : Pass("ice40_ffssr", "iCE40: merge synchronous set/reset into FF cells") { }
  28         void help() YS_OVERRIDE
  29         {
  30                 log("\n");
  31                 log("    ice40_ffssr [options] [selection]\n");
  32                 log("\n");
  33                 log("Merge synchronous set/reset $_MUX_ cells into iCE40 FFs.\n");
  34                 log("\n");
  35         }
  36         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
  37         {
  38                 log_header(design, "Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).\n");
  39
  40                 size_t argidx;
  41                 for (argidx = 1; argidx < args.size(); argidx++)
  42                 {
  43                         // if (args[argidx] == "-singleton") {
  44                         //      singleton_mode = true;
  45                         //      continue;
  46                         // }
  47                         break;
  48                 }
  49                 extra_args(args, argidx, design);
  50
  51                 pool<IdString> sb_dff_types;
  52                 sb_dff_types.insert("\\SB_DFF");
  53                 sb_dff_types.insert("\\SB_DFFE");
  54                 sb_dff_types.insert("\\SB_DFFN");
  55                 sb_dff_types.insert("\\SB_DFFNE");
  56
  57                 for (auto module : design->selected_modules())
  58                 {
  59                         log("Merging set/reset $_MUX_ cells into SB_FFs in %s.\n", log_id(module));
  60
  61                         SigMap sigmap(module);
  62                         dict<SigBit, Cell*> sr_muxes;
  63                         vector<Cell*> ff_cells;
  64
  65                         for (auto cell : module->selected_cells())
  66                         {
  67                                 if (sb_dff_types.count(cell->type)) {
  68                                         ff_cells.push_back(cell);
  69                                         continue;
  70                                 }
  71
  72                                 if (cell->type != "$_MUX_")
  73                                         continue;
  74
  75                                 SigBit bit_a = sigmap(cell->getPort("\\A"));
  76                                 SigBit bit_b = sigmap(cell->getPort("\\B"));
  77
  78                                 if (bit_a.wire == nullptr || bit_b.wire == nullptr)
  79                                         sr_muxes[sigmap(cell->getPort("\\Y"))] = cell;
  80                         }
  81
  82                         for (auto cell : ff_cells)
  83                         {
  84                                 if (cell->get_bool_attribute("\\dont_touch"))
  85                                         continue;
  86
  87                                 SigSpec sig_d = cell->getPort("\\D");
  88
  89                                 if (GetSize(sig_d) < 1)
  90                                         continue;
  91
  92                                 SigBit bit_d = sigmap(sig_d[0]);
  93
  94                                 if (sr_muxes.count(bit_d) == 0)
  95                                         continue;
  96
  97                                 Cell *mux_cell = sr_muxes.at(bit_d);
  98                                 SigBit bit_a = sigmap(mux_cell->getPort("\\A"));
  99                                 SigBit bit_b = sigmap(mux_cell->getPort("\\B"));
 100                                 SigBit bit_s = sigmap(mux_cell->getPort("\\S"));
 101
 102                                 log("  Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
 103                                                 log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));
 104
 105                                 SigBit sr_val, sr_sig;
 106                                 if (bit_a.wire == nullptr) {
 107                                         bit_d = bit_b;
 108                                         sr_val = bit_a;
 109                                         sr_sig = module->NotGate(NEW_ID, bit_s);
 110                                 } else {
 111                                         log_assert(bit_b.wire == nullptr);
 112                                         bit_d = bit_a;
 113                                         sr_val = bit_b;
 114                                         sr_sig = bit_s;
 115                                 }
 116
 117                                 if (sr_val == State::S1) {
 118                                         cell->type = cell->type.str() + "SS";
 119                                         cell->setPort("\\S", sr_sig);
 120                                         cell->setPort("\\D", bit_d);
 121                                 } else {
 122                                         cell->type = cell->type.str() + "SR";
 123                                         cell->setPort("\\R", sr_sig);
 124                                         cell->setPort("\\D", bit_d);
 125                                 }
 126                         }
 127                 }
 128         }
 129 } Ice40FfssrPass;
 130
 131 PRIVATE_NAMESPACE_END