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Try new LUT delays
[yosys.git]
/
techlibs
/
ice40
/
latches_map.v
1
module \$_DLATCH_N_ (E, D, Q);
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wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
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input E, D;
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output Q = !E ? D : Q;
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endmodule
6
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module \$_DLATCH_P_ (E, D, Q);
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wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
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input E, D;
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output Q = E ? D : Q;
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endmodule