2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
26 PRIVATE_NAMESPACE_BEGIN
28 struct SynthIce40Pass
: public ScriptPass
30 SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
32 void help() YS_OVERRIDE
34 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
36 log(" synth_ice40 [options]\n");
38 log("This command runs synthesis for iCE40 FPGAs.\n");
40 log(" -device < hx | lp | u >\n");
41 log(" optimise the synthesis netlist for the specified device.\n");
42 log(" HX is the default target if no device argument specified.\n");
44 log(" -top <module>\n");
45 log(" use the specified module as top module\n");
47 log(" -blif <file>\n");
48 log(" write the design to the specified BLIF file. writing of an output file\n");
49 log(" is omitted if this parameter is not specified.\n");
51 log(" -edif <file>\n");
52 log(" write the design to the specified EDIF file. writing of an output file\n");
53 log(" is omitted if this parameter is not specified.\n");
55 log(" -json <file>\n");
56 log(" write the design to the specified JSON file. writing of an output file\n");
57 log(" is omitted if this parameter is not specified.\n");
59 log(" -run <from_label>:<to_label>\n");
60 log(" only run the commands between the labels (see below). an empty\n");
61 log(" from label is synonymous to 'begin', and empty to label is\n");
62 log(" synonymous to the end of the command list.\n");
65 log(" do not flatten design before synthesis\n");
68 log(" run 'abc' with -dff option\n");
71 log(" combine LUTs after synthesis\n");
74 log(" do not use SB_CARRY cells in output netlist\n");
77 log(" do not use SB_DFFE* cells in output netlist\n");
79 log(" -dffe_min_ce_use <min_ce_use>\n");
80 log(" do not use SB_DFFE* cells if the resulting CE line would go to less\n");
81 log(" than min_ce_use SB_DFFE*in output netlist\n");
84 log(" do not use SB_RAM40_4K* cells in output netlist\n");
87 log(" use iCE40 UltraPlus DSP cells for large arithmetic\n");
90 log(" use built-in Yosys LUT techmapping instead of abc\n");
93 log(" run two passes of 'abc' for slightly improved logic density\n");
96 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
97 log(" (this feature is experimental and incomplete)\n");
100 log(" use abc9 instead of abc\n");
103 log("The following commands are executed by this synthesis command:\n");
109 string top_opt
, blif_file
, edif_file
, json_file
, abc
, device_opt
;
110 bool nocarry
, nodffe
, nobram
, dsp
, flatten
, retime
, relut
, noabc
, abc2
, vpr
;
113 void clear_flags() YS_OVERRIDE
115 top_opt
= "-auto-top";
134 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
136 string run_from
, run_to
;
140 for (argidx
= 1; argidx
< args
.size(); argidx
++)
142 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
143 top_opt
= "-top " + args
[++argidx
];
146 if (args
[argidx
] == "-blif" && argidx
+1 < args
.size()) {
147 blif_file
= args
[++argidx
];
150 if (args
[argidx
] == "-edif" && argidx
+1 < args
.size()) {
151 edif_file
= args
[++argidx
];
154 if (args
[argidx
] == "-json" && argidx
+1 < args
.size()) {
155 json_file
= args
[++argidx
];
158 if (args
[argidx
] == "-run" && argidx
+1 < args
.size()) {
159 size_t pos
= args
[argidx
+1].find(':');
160 if (pos
== std::string::npos
)
162 run_from
= args
[++argidx
].substr(0, pos
);
163 run_to
= args
[argidx
].substr(pos
+1);
166 if (args
[argidx
] == "-flatten") {
170 if (args
[argidx
] == "-noflatten") {
174 if (args
[argidx
] == "-retime") {
178 if (args
[argidx
] == "-relut") {
182 if (args
[argidx
] == "-nocarry") {
186 if (args
[argidx
] == "-nodffe") {
190 if (args
[argidx
] == "-dffe_min_ce_use" && argidx
+1 < args
.size()) {
191 min_ce_use
= std::stoi(args
[++argidx
]);
194 if (args
[argidx
] == "-nobram") {
198 if (args
[argidx
] == "-dsp") {
202 if (args
[argidx
] == "-noabc") {
206 if (args
[argidx
] == "-abc2") {
210 if (args
[argidx
] == "-vpr") {
214 if (args
[argidx
] == "-abc9") {
218 if (args
[argidx
] == "-device" && argidx
+1 < args
.size()) {
219 device_opt
= args
[++argidx
];
224 extra_args(args
, argidx
, design
);
226 if (!design
->full_selection())
227 log_cmd_error("This command only operates on fully selected designs!\n");
228 if (device_opt
!= "hx" && device_opt
!= "lp" && device_opt
!="u")
229 log_cmd_error("Invalid or no device specified: '%s'\n", device_opt
.c_str());
231 log_header(design
, "Executing SYNTH_ICE40 pass.\n");
234 run_script(design
, run_from
, run_to
);
239 void script() YS_OVERRIDE
241 if (check_label("begin"))
243 run("read_verilog -lib -D ABC_MODEL +/ice40/cells_sim.v");
244 run(stringf("hierarchy -check %s", help_mode
? "-top <top>" : top_opt
.c_str()));
248 if (check_label("flatten", "(unless -noflatten)"))
252 run("tribuf -logic");
257 if (check_label("coarse"))
267 run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
270 if (help_mode
|| dsp
)
271 run("ice40_dsp", "(if -dsp)");
276 run("memory -nomap");
280 if (!nobram
&& check_label("bram", "(skip if -nobram)"))
282 run("memory_bram -rules +/ice40/brams.txt");
283 run("techmap -map +/ice40/brams_map.v");
284 run("ice40_braminit");
287 if (check_label("map"))
289 run("opt -fast -mux_undef -undriven -fine");
291 run("opt -undriven -fine");
294 if (check_label("map_gates"))
299 run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
300 if ((retime
|| help_mode
) && abc
!= "abc9")
301 run(abc
+ " -dff", "(only if -retime)");
305 if (check_label("map_ffs"))
309 run("dff2dffe -direct-match $_DFF_*");
310 if (min_ce_use
>= 0) {
312 run(stringf("dff2dffe -unmap-mince %d", min_ce_use
));
314 run("techmap -D NO_LUT -map +/ice40/cells_map.v");
315 run("opt_expr -mux_undef");
319 run("ice40_opt -full");
322 if (check_label("map_luts"))
324 if (abc2
|| help_mode
) {
325 run(abc
, " (only if -abc2)");
326 run("ice40_opt", "(only if -abc2)");
328 run("techmap -map +/ice40/latches_map.v");
329 if (noabc
|| help_mode
) {
330 run("simplemap", " (only if -noabc)");
331 run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
335 run(abc
+ stringf(" -dress -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt
.c_str(), device_opt
.c_str()), "(skip if -noabc)");
337 run(abc
+ " -lut 4", "(skip if -noabc)");
340 if (relut
|| help_mode
) {
341 run("ice40_unlut", " (only if -relut)");
342 run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3", "(only if -relut)");
346 if (check_label("map_cells"))
349 run("techmap -D NO_LUT -map +/ice40/cells_map.v");
351 run("techmap -map +/ice40/cells_map.v", "(with -D NO_LUT in vpr mode)");
356 if (check_label("check"))
358 run("hierarchy -check");
360 run("check -noinit");
363 if (check_label("blif"))
365 if (!blif_file
.empty() || help_mode
) {
366 if (vpr
|| help_mode
) {
367 run(stringf("opt_clean -purge"),
369 run(stringf("write_blif -attr -cname -conn -param %s",
370 help_mode
? "<file-name>" : blif_file
.c_str()),
374 run(stringf("write_blif -gates -attr -param %s",
375 help_mode
? "<file-name>" : blif_file
.c_str()),
380 if (check_label("edif"))
382 if (!edif_file
.empty() || help_mode
)
383 run(stringf("write_edif %s", help_mode
? "<file-name>" : edif_file
.c_str()));
386 if (check_label("json"))
388 if (!json_file
.empty() || help_mode
)
389 run(stringf("write_json %s", help_mode
? "<file-name>" : json_file
.c_str()));
394 PRIVATE_NAMESPACE_END