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Add ice40 box files
[yosys.git] / techlibs / ice40 / synth_ice40.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
24
25 USING_YOSYS_NAMESPACE
26 PRIVATE_NAMESPACE_BEGIN
27
28 struct SynthIce40Pass : public ScriptPass
29 {
30 SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
31
32 void help() YS_OVERRIDE
33 {
34 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
35 log("\n");
36 log(" synth_ice40 [options]\n");
37 log("\n");
38 log("This command runs synthesis for iCE40 FPGAs.\n");
39 log("\n");
40 log(" -top <module>\n");
41 log(" use the specified module as top module\n");
42 log("\n");
43 log(" -blif <file>\n");
44 log(" write the design to the specified BLIF file. writing of an output file\n");
45 log(" is omitted if this parameter is not specified.\n");
46 log("\n");
47 log(" -edif <file>\n");
48 log(" write the design to the specified EDIF file. writing of an output file\n");
49 log(" is omitted if this parameter is not specified.\n");
50 log("\n");
51 log(" -json <file>\n");
52 log(" write the design to the specified JSON file. writing of an output file\n");
53 log(" is omitted if this parameter is not specified.\n");
54 log("\n");
55 log(" -run <from_label>:<to_label>\n");
56 log(" only run the commands between the labels (see below). an empty\n");
57 log(" from label is synonymous to 'begin', and empty to label is\n");
58 log(" synonymous to the end of the command list.\n");
59 log("\n");
60 log(" -noflatten\n");
61 log(" do not flatten design before synthesis\n");
62 log("\n");
63 log(" -retime\n");
64 log(" run 'abc' with -dff option\n");
65 log("\n");
66 log(" -relut\n");
67 log(" combine LUTs after synthesis\n");
68 log("\n");
69 log(" -nocarry\n");
70 log(" do not use SB_CARRY cells in output netlist\n");
71 log("\n");
72 log(" -nodffe\n");
73 log(" do not use SB_DFFE* cells in output netlist\n");
74 log("\n");
75 log(" -dffe_min_ce_use <min_ce_use>\n");
76 log(" do not use SB_DFFE* cells if the resulting CE line would go to less\n");
77 log(" than min_ce_use SB_DFFE*in output netlist\n");
78 log("\n");
79 log(" -nobram\n");
80 log(" do not use SB_RAM40_4K* cells in output netlist\n");
81 log("\n");
82 log(" -dsp\n");
83 log(" use iCE40 UltraPlus DSP cells for large arithmetic\n");
84 log("\n");
85 log(" -noabc\n");
86 log(" use built-in Yosys LUT techmapping instead of abc\n");
87 log("\n");
88 log(" -abc2\n");
89 log(" run two passes of 'abc' for slightly improved logic density\n");
90 log("\n");
91 log(" -vpr\n");
92 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
93 log(" (this feature is experimental and incomplete)\n");
94 log("\n");
95 log(" -abc9\n");
96 log(" use abc9 instead of abc\n");
97 log("\n");
98 log("\n");
99 log("The following commands are executed by this synthesis command:\n");
100 help_script();
101 log("\n");
102 }
103
104
105 string top_opt, blif_file, edif_file, json_file, abc;
106 bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr;
107 int min_ce_use;
108
109 void clear_flags() YS_OVERRIDE
110 {
111 top_opt = "-auto-top";
112 blif_file = "";
113 edif_file = "";
114 json_file = "";
115 nocarry = false;
116 nodffe = false;
117 min_ce_use = -1;
118 nobram = false;
119 dsp = false;
120 flatten = true;
121 retime = false;
122 relut = false;
123 noabc = false;
124 abc2 = false;
125 vpr = false;
126 abc = "abc";
127 }
128
129 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
130 {
131 string run_from, run_to;
132 clear_flags();
133
134 size_t argidx;
135 for (argidx = 1; argidx < args.size(); argidx++)
136 {
137 if (args[argidx] == "-top" && argidx+1 < args.size()) {
138 top_opt = "-top " + args[++argidx];
139 continue;
140 }
141 if (args[argidx] == "-blif" && argidx+1 < args.size()) {
142 blif_file = args[++argidx];
143 continue;
144 }
145 if (args[argidx] == "-edif" && argidx+1 < args.size()) {
146 edif_file = args[++argidx];
147 continue;
148 }
149 if (args[argidx] == "-json" && argidx+1 < args.size()) {
150 json_file = args[++argidx];
151 continue;
152 }
153 if (args[argidx] == "-run" && argidx+1 < args.size()) {
154 size_t pos = args[argidx+1].find(':');
155 if (pos == std::string::npos)
156 break;
157 run_from = args[++argidx].substr(0, pos);
158 run_to = args[argidx].substr(pos+1);
159 continue;
160 }
161 if (args[argidx] == "-flatten") {
162 flatten = true;
163 continue;
164 }
165 if (args[argidx] == "-noflatten") {
166 flatten = false;
167 continue;
168 }
169 if (args[argidx] == "-retime") {
170 retime = true;
171 continue;
172 }
173 if (args[argidx] == "-relut") {
174 relut = true;
175 continue;
176 }
177 if (args[argidx] == "-nocarry") {
178 nocarry = true;
179 continue;
180 }
181 if (args[argidx] == "-nodffe") {
182 nodffe = true;
183 continue;
184 }
185 if (args[argidx] == "-dffe_min_ce_use" && argidx+1 < args.size()) {
186 min_ce_use = std::stoi(args[++argidx]);
187 continue;
188 }
189 if (args[argidx] == "-nobram") {
190 nobram = true;
191 continue;
192 }
193 if (args[argidx] == "-dsp") {
194 dsp = true;
195 continue;
196 }
197 if (args[argidx] == "-noabc") {
198 noabc = true;
199 continue;
200 }
201 if (args[argidx] == "-abc2") {
202 abc2 = true;
203 continue;
204 }
205 if (args[argidx] == "-vpr") {
206 vpr = true;
207 continue;
208 }
209 if (args[argidx] == "-abc9") {
210 abc = "abc9";
211 continue;
212 }
213 break;
214 }
215 extra_args(args, argidx, design);
216
217 if (!design->full_selection())
218 log_cmd_error("This command only operates on fully selected designs!\n");
219
220 log_header(design, "Executing SYNTH_ICE40 pass.\n");
221 log_push();
222
223 run_script(design, run_from, run_to);
224
225 log_pop();
226 }
227
228 void script() YS_OVERRIDE
229 {
230 if (check_label("begin"))
231 {
232 run("read_verilog -lib +/ice40/cells_sim.v");
233 run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
234 run("proc");
235 }
236
237 if (flatten && check_label("flatten", "(unless -noflatten)"))
238 {
239 run("flatten");
240 run("tribuf -logic");
241 run("deminout");
242 }
243
244 if (check_label("coarse"))
245 {
246 run("opt_expr");
247 run("opt_clean");
248 run("check");
249 run("opt");
250 run("wreduce");
251 run("share");
252 run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
253 run("opt_expr");
254 run("opt_clean");
255 if (help_mode || dsp)
256 run("ice40_dsp", "(if -dsp)");
257 run("alumacc");
258 run("opt");
259 run("fsm");
260 run("opt -fast");
261 run("memory -nomap");
262 run("opt_clean");
263 }
264
265 if (!nobram && check_label("bram", "(skip if -nobram)"))
266 {
267 run("memory_bram -rules +/ice40/brams.txt");
268 run("techmap -map +/ice40/brams_map.v");
269 run("ice40_braminit");
270 }
271
272 if (check_label("map"))
273 {
274 run("opt -fast -mux_undef -undriven -fine");
275 run("memory_map");
276 run("opt -undriven -fine");
277 }
278
279 if (check_label("map_gates"))
280 {
281 if (nocarry)
282 run("techmap");
283 else
284 run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
285 if (retime || help_mode)
286 run(abc + " -dff", "(only if -retime)");
287 run("ice40_opt");
288 }
289
290 if (check_label("map_ffs"))
291 {
292 run("dffsr2dff");
293 if (!nodffe)
294 run("dff2dffe -direct-match $_DFF_*");
295 if (min_ce_use >= 0) {
296 run("opt_merge");
297 run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
298 }
299 run("techmap -D NO_LUT -map +/ice40/cells_map.v");
300 run("opt_expr -mux_undef");
301 run("simplemap");
302 run("ice40_ffinit");
303 run("ice40_ffssr");
304 run("ice40_opt -full");
305 }
306
307 if (check_label("map_luts"))
308 {
309 if (abc2 || help_mode) {
310 run(abc, " (only if -abc2)");
311 run("ice40_opt", "(only if -abc2)");
312 }
313 run("techmap -map +/ice40/latches_map.v");
314 if (noabc || help_mode) {
315 run("simplemap", " (only if -noabc)");
316 run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
317 }
318 if (!noabc) {
319 if (abc == "abc9") {
320 run("read_verilog +/ice40/cells_box.v");
321 run("techmap -map +/techmap.v A:abc_box_id");
322 run(abc + " -dress -lut +/ice40/lut.lut -box +/ice40/cells.box", "(skip if -noabc)");
323 run("blackbox A:abc_box_id");
324 }
325 else
326 run(abc + " -lut 4", "(skip if -noabc)");
327 }
328 run("clean");
329 if (relut || help_mode) {
330 run("ice40_unlut", " (only if -relut)");
331 run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3", "(only if -relut)");
332 }
333 }
334
335 if (check_label("map_cells"))
336 {
337 if (vpr)
338 run("techmap -D NO_LUT -map +/ice40/cells_map.v");
339 else
340 run("techmap -map +/ice40/cells_map.v", "(with -D NO_LUT in vpr mode)");
341
342 run("clean");
343 }
344
345 if (check_label("check"))
346 {
347 run("hierarchy -check");
348 run("stat");
349 run("check -noinit");
350 }
351
352 if (check_label("blif"))
353 {
354 if (!blif_file.empty() || help_mode) {
355 if (vpr || help_mode) {
356 run(stringf("opt_clean -purge"),
357 " (vpr mode)");
358 run(stringf("write_blif -attr -cname -conn -param %s",
359 help_mode ? "<file-name>" : blif_file.c_str()),
360 " (vpr mode)");
361 }
362 if (!vpr)
363 run(stringf("write_blif -gates -attr -param %s",
364 help_mode ? "<file-name>" : blif_file.c_str()),
365 " (non-vpr mode)");
366 }
367 }
368
369 if (check_label("edif"))
370 {
371 if (!edif_file.empty() || help_mode)
372 run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
373 }
374
375 if (check_label("json"))
376 {
377 if (!json_file.empty() || help_mode)
378 run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
379 }
380 }
381 } SynthIce40Pass;
382
383 PRIVATE_NAMESPACE_END