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Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
[yosys.git] / techlibs / ice40 / synth_ice40.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
24
25 USING_YOSYS_NAMESPACE
26 PRIVATE_NAMESPACE_BEGIN
27
28 struct SynthIce40Pass : public ScriptPass
29 {
30 SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
31
32 void help() YS_OVERRIDE
33 {
34 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
35 log("\n");
36 log(" synth_ice40 [options]\n");
37 log("\n");
38 log("This command runs synthesis for iCE40 FPGAs.\n");
39 log("\n");
40 log(" -device < hx | lp | u >\n");
41 log(" optimise the synthesis netlist for the specified device.\n");
42 log(" HX is the default target if no device argument specified.\n");
43 log("\n");
44 log(" -top <module>\n");
45 log(" use the specified module as top module\n");
46 log("\n");
47 log(" -blif <file>\n");
48 log(" write the design to the specified BLIF file. writing of an output file\n");
49 log(" is omitted if this parameter is not specified.\n");
50 log("\n");
51 log(" -edif <file>\n");
52 log(" write the design to the specified EDIF file. writing of an output file\n");
53 log(" is omitted if this parameter is not specified.\n");
54 log("\n");
55 log(" -json <file>\n");
56 log(" write the design to the specified JSON file. writing of an output file\n");
57 log(" is omitted if this parameter is not specified.\n");
58 log("\n");
59 log(" -run <from_label>:<to_label>\n");
60 log(" only run the commands between the labels (see below). an empty\n");
61 log(" from label is synonymous to 'begin', and empty to label is\n");
62 log(" synonymous to the end of the command list.\n");
63 log("\n");
64 log(" -noflatten\n");
65 log(" do not flatten design before synthesis\n");
66 log("\n");
67 log(" -retime\n");
68 log(" run 'abc' with -dff option\n");
69 log("\n");
70 log(" -relut\n");
71 log(" combine LUTs after synthesis\n");
72 log("\n");
73 log(" -nocarry\n");
74 log(" do not use SB_CARRY cells in output netlist\n");
75 log("\n");
76 log(" -nodffe\n");
77 log(" do not use SB_DFFE* cells in output netlist\n");
78 log("\n");
79 log(" -dffe_min_ce_use <min_ce_use>\n");
80 log(" do not use SB_DFFE* cells if the resulting CE line would go to less\n");
81 log(" than min_ce_use SB_DFFE*in output netlist\n");
82 log("\n");
83 log(" -nobram\n");
84 log(" do not use SB_RAM40_4K* cells in output netlist\n");
85 log("\n");
86 log(" -dsp\n");
87 log(" use iCE40 UltraPlus DSP cells for large arithmetic\n");
88 log("\n");
89 log(" -noabc\n");
90 log(" use built-in Yosys LUT techmapping instead of abc\n");
91 log("\n");
92 log(" -abc2\n");
93 log(" run two passes of 'abc' for slightly improved logic density\n");
94 log("\n");
95 log(" -vpr\n");
96 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
97 log(" (this feature is experimental and incomplete)\n");
98 log("\n");
99 log(" -abc9\n");
100 log(" use abc9 instead of abc\n");
101 log("\n");
102 log("\n");
103 log("The following commands are executed by this synthesis command:\n");
104 help_script();
105 log("\n");
106 }
107
108
109 string top_opt, blif_file, edif_file, json_file, abc, device_opt;
110 bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr;
111 int min_ce_use;
112
113 void clear_flags() YS_OVERRIDE
114 {
115 top_opt = "-auto-top";
116 blif_file = "";
117 edif_file = "";
118 json_file = "";
119 nocarry = false;
120 nodffe = false;
121 min_ce_use = -1;
122 nobram = false;
123 dsp = false;
124 flatten = true;
125 retime = false;
126 relut = false;
127 noabc = false;
128 abc2 = false;
129 vpr = false;
130 abc = "abc";
131 device_opt = "hx";
132 }
133
134 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
135 {
136 string run_from, run_to;
137 clear_flags();
138
139 size_t argidx;
140 for (argidx = 1; argidx < args.size(); argidx++)
141 {
142 if (args[argidx] == "-top" && argidx+1 < args.size()) {
143 top_opt = "-top " + args[++argidx];
144 continue;
145 }
146 if (args[argidx] == "-blif" && argidx+1 < args.size()) {
147 blif_file = args[++argidx];
148 continue;
149 }
150 if (args[argidx] == "-edif" && argidx+1 < args.size()) {
151 edif_file = args[++argidx];
152 continue;
153 }
154 if (args[argidx] == "-json" && argidx+1 < args.size()) {
155 json_file = args[++argidx];
156 continue;
157 }
158 if (args[argidx] == "-run" && argidx+1 < args.size()) {
159 size_t pos = args[argidx+1].find(':');
160 if (pos == std::string::npos)
161 break;
162 run_from = args[++argidx].substr(0, pos);
163 run_to = args[argidx].substr(pos+1);
164 continue;
165 }
166 if (args[argidx] == "-flatten") {
167 flatten = true;
168 continue;
169 }
170 if (args[argidx] == "-noflatten") {
171 flatten = false;
172 continue;
173 }
174 if (args[argidx] == "-retime") {
175 retime = true;
176 continue;
177 }
178 if (args[argidx] == "-relut") {
179 relut = true;
180 continue;
181 }
182 if (args[argidx] == "-nocarry") {
183 nocarry = true;
184 continue;
185 }
186 if (args[argidx] == "-nodffe") {
187 nodffe = true;
188 continue;
189 }
190 if (args[argidx] == "-dffe_min_ce_use" && argidx+1 < args.size()) {
191 min_ce_use = std::stoi(args[++argidx]);
192 continue;
193 }
194 if (args[argidx] == "-nobram") {
195 nobram = true;
196 continue;
197 }
198 if (args[argidx] == "-dsp") {
199 dsp = true;
200 continue;
201 }
202 if (args[argidx] == "-noabc") {
203 noabc = true;
204 continue;
205 }
206 if (args[argidx] == "-abc2") {
207 abc2 = true;
208 continue;
209 }
210 if (args[argidx] == "-vpr") {
211 vpr = true;
212 continue;
213 }
214 if (args[argidx] == "-abc9") {
215 abc = "abc9";
216 continue;
217 }
218 if (args[argidx] == "-device" && argidx+1 < args.size()) {
219 device_opt = args[++argidx];
220 continue;
221 }
222 break;
223 }
224 extra_args(args, argidx, design);
225
226 if (!design->full_selection())
227 log_cmd_error("This command only operates on fully selected designs!\n");
228 if (device_opt != "hx" && device_opt != "lp" && device_opt !="u")
229 log_cmd_error("Invalid or no device specified: '%s'\n", device_opt.c_str());
230
231 log_header(design, "Executing SYNTH_ICE40 pass.\n");
232 log_push();
233
234 run_script(design, run_from, run_to);
235
236 log_pop();
237 }
238
239 void script() YS_OVERRIDE
240 {
241 if (check_label("begin"))
242 {
243 run("read_verilog -lib -D_ABC +/ice40/cells_sim.v");
244 run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
245 run("proc");
246 }
247
248 if (check_label("flatten", "(unless -noflatten)"))
249 {
250 if (flatten) {
251 run("flatten");
252 run("tribuf -logic");
253 run("deminout");
254 }
255 }
256
257 if (check_label("coarse"))
258 {
259 run("opt_expr");
260 run("opt_clean");
261 run("check");
262 run("opt");
263 run("wreduce");
264 run("peepopt");
265 run("opt_clean");
266 run("share");
267 run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
268 run("opt_expr");
269 run("opt_clean");
270 if (help_mode || dsp)
271 run("ice40_dsp", "(if -dsp)");
272 run("alumacc");
273 run("opt");
274 run("fsm");
275 run("opt -fast");
276 run("memory -nomap");
277 run("opt_clean");
278 }
279
280 if (!nobram && check_label("bram", "(skip if -nobram)"))
281 {
282 run("memory_bram -rules +/ice40/brams.txt");
283 run("techmap -map +/ice40/brams_map.v");
284 run("ice40_braminit");
285 }
286
287 if (check_label("map"))
288 {
289 run("opt -fast -mux_undef -undriven -fine");
290 run("memory_map");
291 run("opt -undriven -fine");
292 }
293
294 if (check_label("map_gates"))
295 {
296 if (nocarry)
297 run("techmap");
298 else
299 run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
300 if ((retime || help_mode) && abc != "abc9")
301 run(abc + " -dff", "(only if -retime)");
302 run("ice40_opt");
303 }
304
305 if (check_label("map_ffs"))
306 {
307 run("dffsr2dff");
308 if (!nodffe)
309 run("dff2dffe -direct-match $_DFF_*");
310 if (min_ce_use >= 0) {
311 run("opt_merge");
312 run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
313 }
314 run("techmap -D NO_LUT -map +/ice40/cells_map.v");
315 run("opt_expr -mux_undef");
316 run("simplemap");
317 run("ice40_ffinit");
318 run("ice40_ffssr");
319 run("ice40_opt -full");
320 }
321
322 if (check_label("map_luts"))
323 {
324 if (abc2 || help_mode) {
325 run(abc, " (only if -abc2)");
326 run("ice40_opt", "(only if -abc2)");
327 }
328 run("techmap -map +/ice40/latches_map.v");
329 if (noabc || help_mode) {
330 run("simplemap", " (only if -noabc)");
331 run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
332 }
333 if (!noabc) {
334 if (abc == "abc9")
335 run(abc + stringf(" -dress -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
336 else
337 run(abc + " -dress -lut 4", "(skip if -noabc)");
338 }
339 run("clean");
340 if (relut || help_mode) {
341 run("ice40_unlut", " (only if -relut)");
342 run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3", "(only if -relut)");
343 }
344 }
345
346 if (check_label("map_cells"))
347 {
348 if (vpr)
349 run("techmap -D NO_LUT -map +/ice40/cells_map.v");
350 else
351 run("techmap -map +/ice40/cells_map.v", "(with -D NO_LUT in vpr mode)");
352
353 run("clean");
354 }
355
356 if (check_label("check"))
357 {
358 run("hierarchy -check");
359 run("stat");
360 run("check -noinit");
361 }
362
363 if (check_label("blif"))
364 {
365 if (!blif_file.empty() || help_mode) {
366 if (vpr || help_mode) {
367 run(stringf("opt_clean -purge"),
368 " (vpr mode)");
369 run(stringf("write_blif -attr -cname -conn -param %s",
370 help_mode ? "<file-name>" : blif_file.c_str()),
371 " (vpr mode)");
372 }
373 if (!vpr)
374 run(stringf("write_blif -gates -attr -param %s",
375 help_mode ? "<file-name>" : blif_file.c_str()),
376 " (non-vpr mode)");
377 }
378 }
379
380 if (check_label("edif"))
381 {
382 if (!edif_file.empty() || help_mode)
383 run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
384 }
385
386 if (check_label("json"))
387 {
388 if (!json_file.empty() || help_mode)
389 run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
390 }
391 }
392 } SynthIce40Pass;
393
394 PRIVATE_NAMESPACE_END