techlibs/ice40/synth_ice40.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
  29 {
  30         if (label == run_from)
  31                 active = true;
  32         if (label == run_to)
  33                 active = false;
  34         return active;
  35 }
  36
  37 struct SynthIce40Pass : public Pass {
  38         SynthIce40Pass() : Pass("synth_ice40", "synthesis for iCE40 FPGAs") { }
  39         virtual void help()
  40         {
  41                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  42                 log("\n");
  43                 log("    synth_ice40 [options]\n");
  44                 log("\n");
  45                 log("This command runs synthesis for iCE40 FPGAs. This work is experimental.\n");
  46                 log("\n");
  47                 log("    -top <module>\n");
  48                 log("        use the specified module as top module (default='top')\n");
  49                 log("\n");
  50                 log("    -blif <file>\n");
  51                 log("        write the design to the specified BLIF file. writing of an output file\n");
  52                 log("        is omitted if this parameter is not specified.\n");
  53                 log("\n");
  54                 log("    -edif <file>\n");
  55                 log("        write the design to the specified edif file. writing of an output file\n");
  56                 log("        is omitted if this parameter is not specified.\n");
  57                 log("\n");
  58                 log("    -run <from_label>:<to_label>\n");
  59                 log("        only run the commands between the labels (see below). an empty\n");
  60                 log("        from label is synonymous to 'begin', and empty to label is\n");
  61                 log("        synonymous to the end of the command list.\n");
  62                 log("\n");
  63                 log("    -noflatten\n");
  64                 log("        do not flatten design before synthesis\n");
  65                 log("\n");
  66                 log("    -retime\n");
  67                 log("        run 'abc' with -dff option\n");
  68                 log("\n");
  69                 log("    -nocarry\n");
  70                 log("        do not use SB_CARRY cells in output netlist\n");
  71                 log("\n");
  72                 log("    -nobram\n");
  73                 log("        do not use SB_RAM40_4K* cells in output netlist\n");
  74                 log("\n");
  75                 log("\n");
  76                 log("The following commands are executed by this synthesis command:\n");
  77                 log("\n");
  78                 log("    begin:\n");
  79                 log("        read_verilog -lib +/ice40/cells_sim.v\n");
  80                 log("        hierarchy -check -top <top>\n");
  81                 log("\n");
  82                 log("    flatten:         (unless -noflatten)\n");
  83                 log("        proc\n");
  84                 log("        flatten\n");
  85                 log("        tribuf -logic\n");
  86                 log("\n");
  87                 log("    coarse:\n");
  88                 log("        synth -run coarse\n");
  89                 log("\n");
  90                 log("    bram:            (skip if -nobram)\n");
  91                 log("        memory_bram -rules +/ice40/brams.txt\n");
  92                 log("        techmap -map +/ice40/brams_map.v\n");
  93                 log("\n");
  94                 log("    fine:\n");
  95                 log("        opt -fast -mux_undef -undriven -fine\n");
  96                 log("        memory_map\n");
  97                 log("        opt -undriven -fine\n");
  98                 log("        techmap -map +/techmap.v [-map +/ice40/arith_map.v]\n");
  99                 log("        abc -dff     (only if -retime)\n");
 100                 log("        ice40_opt\n");
 101                 log("\n");
 102                 log("    map_ffs:\n");
 103                 log("        dff2dffe -direct-match $_DFF_*\n");
 104                 log("        techmap -map +/ice40/cells_map.v\n");
 105                 log("        opt_const -mux_undef\n");
 106                 log("        simplemap\n");
 107                 log("        ice40_ffinit\n");
 108                 log("        ice40_ffssr\n");
 109                 log("        ice40_opt -full\n");
 110                 log("\n");
 111                 log("    map_luts:\n");
 112                 log("        abc -lut 4\n");
 113                 log("        clean\n");
 114                 log("\n");
 115                 log("    map_cells:\n");
 116                 log("        techmap -map +/ice40/cells_map.v\n");
 117                 log("        clean\n");
 118                 log("\n");
 119                 log("    check:\n");
 120                 log("        hierarchy -check\n");
 121                 log("        stat\n");
 122                 log("        check -noinit\n");
 123                 log("\n");
 124                 log("    blif:\n");
 125                 log("        write_blif -gates -attr -param <file-name>\n");
 126                 log("\n");
 127                 log("    edif:\n");
 128                 log("        write_edif <file-name>\n");
 129                 log("\n");
 130         }
 131         virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 132         {
 133                 std::string top_opt = "-auto-top";
 134                 std::string run_from, run_to;
 135                 std::string blif_file, edif_file;
 136                 bool nocarry = false;
 137                 bool nobram = false;
 138                 bool flatten = true;
 139                 bool retime = false;
 140
 141                 size_t argidx;
 142                 for (argidx = 1; argidx < args.size(); argidx++)
 143                 {
 144                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
 145                                 top_opt = "-top " + args[++argidx];
 146                                 continue;
 147                         }
 148                         if (args[argidx] == "-blif" && argidx+1 < args.size()) {
 149                                 blif_file = args[++argidx];
 150                                 continue;
 151                         }
 152                         if (args[argidx] == "-edif" && argidx+1 < args.size()) {
 153                                 edif_file = args[++argidx];
 154                                 continue;
 155                         }
 156                         if (args[argidx] == "-run" && argidx+1 < args.size()) {
 157                                 size_t pos = args[argidx+1].find(':');
 158                                 if (pos == std::string::npos)
 159                                         break;
 160                                 run_from = args[++argidx].substr(0, pos);
 161                                 run_to = args[argidx].substr(pos+1);
 162                                 continue;
 163                         }
 164                         if (args[argidx] == "-flatten") {
 165                                 flatten = true;
 166                                 continue;
 167                         }
 168                         if (args[argidx] == "-noflatten") {
 169                                 flatten = false;
 170                                 continue;
 171                         }
 172                         if (args[argidx] == "-retime") {
 173                                 retime = true;
 174                                 continue;
 175                         }
 176                         if (args[argidx] == "-nocarry") {
 177                                 nocarry = true;
 178                                 continue;
 179                         }
 180                         if (args[argidx] == "-nobram") {
 181                                 nobram = true;
 182                                 continue;
 183                         }
 184                         break;
 185                 }
 186                 extra_args(args, argidx, design);
 187
 188                 if (!design->full_selection())
 189                         log_cmd_error("This comannd only operates on fully selected designs!\n");
 190
 191                 bool active = run_from.empty();
 192
 193                 log_header("Executing SYNTH_ICE40 pass.\n");
 194                 log_push();
 195
 196                 if (check_label(active, run_from, run_to, "begin"))
 197                 {
 198                         Pass::call(design, "read_verilog -lib +/ice40/cells_sim.v");
 199                         Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str()));
 200                 }
 201
 202                 if (flatten && check_label(active, run_from, run_to, "flatten"))
 203                 {
 204                         Pass::call(design, "proc");
 205                         Pass::call(design, "flatten");
 206                         Pass::call(design, "tribuf -logic");
 207                 }
 208
 209                 if (check_label(active, run_from, run_to, "coarse"))
 210                 {
 211                         Pass::call(design, "synth -run coarse");
 212                 }
 213
 214                 if (!nobram && check_label(active, run_from, run_to, "bram"))
 215                 {
 216                         Pass::call(design, "memory_bram -rules +/ice40/brams.txt");
 217                         Pass::call(design, "techmap -map +/ice40/brams_map.v");
 218                 }
 219
 220                 if (check_label(active, run_from, run_to, "fine"))
 221                 {
 222                         Pass::call(design, "opt -fast -mux_undef -undriven -fine");
 223                         Pass::call(design, "memory_map");
 224                         Pass::call(design, "opt -undriven -fine");
 225                         if (nocarry)
 226                                 Pass::call(design, "techmap");
 227                         else
 228                                 Pass::call(design, "techmap -map +/techmap.v -map +/ice40/arith_map.v");
 229                         if (retime)
 230                                 Pass::call(design, "abc -dff");
 231                         Pass::call(design, "ice40_opt");
 232                 }
 233
 234                 if (check_label(active, run_from, run_to, "map_ffs"))
 235                 {
 236                         Pass::call(design, "dff2dffe -direct-match $_DFF_*");
 237                         Pass::call(design, "techmap -map +/ice40/cells_map.v");
 238                         Pass::call(design, "opt_const -mux_undef");
 239                         Pass::call(design, "simplemap");
 240                         Pass::call(design, "ice40_ffinit");
 241                         Pass::call(design, "ice40_ffssr");
 242                         Pass::call(design, "ice40_opt -full");
 243                 }
 244
 245                 if (check_label(active, run_from, run_to, "map_luts"))
 246                 {
 247                         Pass::call(design, "abc -lut 4");
 248                         Pass::call(design, "clean");
 249                 }
 250
 251                 if (check_label(active, run_from, run_to, "map_cells"))
 252                 {
 253                         Pass::call(design, "techmap -map +/ice40/cells_map.v");
 254                         Pass::call(design, "clean");
 255                 }
 256
 257                 if (check_label(active, run_from, run_to, "check"))
 258                 {
 259                         Pass::call(design, "hierarchy -check");
 260                         Pass::call(design, "stat");
 261                         Pass::call(design, "check -noinit");
 262                 }
 263
 264                 if (check_label(active, run_from, run_to, "blif"))
 265                 {
 266                         if (!blif_file.empty())
 267                                 Pass::call(design, stringf("write_blif -gates -attr -param %s", blif_file.c_str()));
 268                 }
 269
 270                 if (check_label(active, run_from, run_to, "edif"))
 271                 {
 272                         if (!edif_file.empty())
 273                                 Pass::call(design, stringf("write_edif %s", edif_file.c_str()));
 274                 }
 275
 276                 log_pop();
 277         }
 278 } SynthIce40Pass;
 279
 280 PRIVATE_NAMESPACE_END