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d92e407262e76c1eba194b78ee8d80ec697bf25e
[yosys.git] / techlibs / ice40 / synth_ice40.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
24
25 USING_YOSYS_NAMESPACE
26 PRIVATE_NAMESPACE_BEGIN
27
28 struct SynthIce40Pass : public ScriptPass
29 {
30 SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
31
32 void help() YS_OVERRIDE
33 {
34 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
35 log("\n");
36 log(" synth_ice40 [options]\n");
37 log("\n");
38 log("This command runs synthesis for iCE40 FPGAs.\n");
39 log("\n");
40 log(" -device < hx | lp | u >\n");
41 log(" relevant only for '-abc9' flow, optimise timing for the specified device.\n");
42 log(" default: hx\n");
43 log("\n");
44 log(" -top <module>\n");
45 log(" use the specified module as top module\n");
46 log("\n");
47 log(" -blif <file>\n");
48 log(" write the design to the specified BLIF file. writing of an output file\n");
49 log(" is omitted if this parameter is not specified.\n");
50 log("\n");
51 log(" -edif <file>\n");
52 log(" write the design to the specified EDIF file. writing of an output file\n");
53 log(" is omitted if this parameter is not specified.\n");
54 log("\n");
55 log(" -json <file>\n");
56 log(" write the design to the specified JSON file. writing of an output file\n");
57 log(" is omitted if this parameter is not specified.\n");
58 log("\n");
59 log(" -run <from_label>:<to_label>\n");
60 log(" only run the commands between the labels (see below). an empty\n");
61 log(" from label is synonymous to 'begin', and empty to label is\n");
62 log(" synonymous to the end of the command list.\n");
63 log("\n");
64 log(" -noflatten\n");
65 log(" do not flatten design before synthesis\n");
66 log("\n");
67 log(" -retime\n");
68 log(" run 'abc' with '-dff -D 1' options\n");
69 log("\n");
70 log(" -nocarry\n");
71 log(" do not use SB_CARRY cells in output netlist\n");
72 log("\n");
73 log(" -nodffe\n");
74 log(" do not use SB_DFFE* cells in output netlist\n");
75 log("\n");
76 log(" -dffe_min_ce_use <min_ce_use>\n");
77 log(" do not use SB_DFFE* cells if the resulting CE line would go to less\n");
78 log(" than min_ce_use SB_DFFE* in output netlist\n");
79 log("\n");
80 log(" -nobram\n");
81 log(" do not use SB_RAM40_4K* cells in output netlist\n");
82 log("\n");
83 log(" -dsp\n");
84 log(" use iCE40 UltraPlus DSP cells for large arithmetic\n");
85 log("\n");
86 log(" -noabc\n");
87 log(" use built-in Yosys LUT techmapping instead of abc\n");
88 log("\n");
89 log(" -abc2\n");
90 log(" run two passes of 'abc' for slightly improved logic density\n");
91 log("\n");
92 log(" -vpr\n");
93 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
94 log(" (this feature is experimental and incomplete)\n");
95 log("\n");
96 log(" -abc9\n");
97 log(" use new ABC9 flow (EXPERIMENTAL)\n");
98 log("\n");
99 log("\n");
100 log("The following commands are executed by this synthesis command:\n");
101 help_script();
102 log("\n");
103 }
104
105 string top_opt, blif_file, edif_file, json_file, device_opt;
106 bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr, abc9;
107 int min_ce_use;
108
109 void clear_flags() YS_OVERRIDE
110 {
111 top_opt = "-auto-top";
112 blif_file = "";
113 edif_file = "";
114 json_file = "";
115 nocarry = false;
116 nodffe = false;
117 min_ce_use = -1;
118 nobram = false;
119 dsp = false;
120 flatten = true;
121 retime = false;
122 noabc = false;
123 abc2 = false;
124 vpr = false;
125 abc9 = false;
126 device_opt = "hx";
127 }
128
129 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
130 {
131 string run_from, run_to;
132 clear_flags();
133
134 size_t argidx;
135 for (argidx = 1; argidx < args.size(); argidx++)
136 {
137 if (args[argidx] == "-top" && argidx+1 < args.size()) {
138 top_opt = "-top " + args[++argidx];
139 continue;
140 }
141 if (args[argidx] == "-blif" && argidx+1 < args.size()) {
142 blif_file = args[++argidx];
143 continue;
144 }
145 if (args[argidx] == "-edif" && argidx+1 < args.size()) {
146 edif_file = args[++argidx];
147 continue;
148 }
149 if (args[argidx] == "-json" && argidx+1 < args.size()) {
150 json_file = args[++argidx];
151 continue;
152 }
153 if (args[argidx] == "-run" && argidx+1 < args.size()) {
154 size_t pos = args[argidx+1].find(':');
155 if (pos == std::string::npos)
156 break;
157 run_from = args[++argidx].substr(0, pos);
158 run_to = args[argidx].substr(pos+1);
159 continue;
160 }
161 if (args[argidx] == "-flatten") {
162 flatten = true;
163 continue;
164 }
165 if (args[argidx] == "-noflatten") {
166 flatten = false;
167 continue;
168 }
169 if (args[argidx] == "-retime") {
170 retime = true;
171 continue;
172 }
173 if (args[argidx] == "-relut") {
174 // removed, opt_lut is always run
175 continue;
176 }
177 if (args[argidx] == "-nocarry") {
178 nocarry = true;
179 continue;
180 }
181 if (args[argidx] == "-nodffe") {
182 nodffe = true;
183 continue;
184 }
185 if (args[argidx] == "-dffe_min_ce_use" && argidx+1 < args.size()) {
186 min_ce_use = atoi(args[++argidx].c_str());
187 continue;
188 }
189 if (args[argidx] == "-nobram") {
190 nobram = true;
191 continue;
192 }
193 if (args[argidx] == "-dsp") {
194 dsp = true;
195 continue;
196 }
197 if (args[argidx] == "-noabc") {
198 noabc = true;
199 continue;
200 }
201 if (args[argidx] == "-abc2") {
202 abc2 = true;
203 continue;
204 }
205 if (args[argidx] == "-vpr") {
206 vpr = true;
207 continue;
208 }
209 if (args[argidx] == "-abc9") {
210 abc9 = true;
211 continue;
212 }
213 if (args[argidx] == "-device" && argidx+1 < args.size()) {
214 device_opt = args[++argidx];
215 continue;
216 }
217 break;
218 }
219 extra_args(args, argidx, design);
220
221 if (!design->full_selection())
222 log_cmd_error("This command only operates on fully selected designs!\n");
223 if (device_opt != "hx" && device_opt != "lp" && device_opt !="u")
224 log_cmd_error("Invalid or no device specified: '%s'\n", device_opt.c_str());
225
226 if (abc9 && retime)
227 log_cmd_error("-retime option not currently compatible with -abc9!\n");
228
229 log_header(design, "Executing SYNTH_ICE40 pass.\n");
230 log_push();
231
232 run_script(design, run_from, run_to);
233
234 log_pop();
235 }
236
237 void script() YS_OVERRIDE
238 {
239 if (check_label("begin"))
240 {
241 std::string define;
242 if (device_opt == "lp")
243 define = "-D ICE40_LP";
244 else if (device_opt == "u")
245 define = "-D ICE40_U";
246 else
247 define = "-D ICE40_HX";
248 run("read_verilog " + define + " -lib +/ice40/cells_sim.v");
249 run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
250 run("proc");
251 }
252
253 if (check_label("flatten", "(unless -noflatten)"))
254 {
255 if (flatten) {
256 run("flatten");
257 run("tribuf -logic");
258 run("deminout");
259 }
260 }
261
262 if (check_label("coarse"))
263 {
264 run("opt_expr");
265 run("opt_clean");
266 run("check");
267 run("opt");
268 run("wreduce");
269 run("peepopt");
270 run("opt_clean");
271 run("share");
272 run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
273 run("opt_expr");
274 run("opt_clean");
275 if (help_mode || dsp) {
276 run("memory_dff"); // ice40_dsp will merge registers, reserve memory port registers first
277 run("wreduce t:$mul");
278 run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
279 "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
280 "-D DSP_NAME=$__MUL16X16", "(if -dsp)");
281 run("select a:mul2dsp", " (if -dsp)");
282 run("setattr -unset mul2dsp", " (if -dsp)");
283 run("opt_expr -fine", " (if -dsp)");
284 run("wreduce", " (if -dsp)");
285 run("select -clear", " (if -dsp)");
286 run("ice40_dsp", " (if -dsp)");
287 run("chtype -set $mul t:$__soft_mul", "(if -dsp)");
288 }
289 run("alumacc");
290 run("opt");
291 run("fsm");
292 run("opt -fast");
293 run("memory -nomap");
294 run("opt_clean");
295 }
296
297 if (!nobram && check_label("map_bram", "(skip if -nobram)"))
298 {
299 run("memory_bram -rules +/ice40/brams.txt");
300 run("techmap -map +/ice40/brams_map.v");
301 run("ice40_braminit");
302 }
303
304 if (check_label("map_ffram"))
305 {
306 run("opt -fast -mux_undef -undriven -fine");
307 run("memory_map");
308 run("opt -undriven -fine");
309 }
310
311 if (check_label("map_gates"))
312 {
313 if (nocarry)
314 run("techmap");
315 else {
316 run("ice40_wrapcarry");
317 run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
318 }
319 if (retime || help_mode)
320 run("abc -dff -D 1", "(only if -retime)");
321 run("ice40_opt");
322 }
323
324 if (check_label("map_ffs"))
325 {
326 run("dffsr2dff");
327 if (!nodffe)
328 run("dff2dffe -direct-match $_DFF_*");
329 if (min_ce_use >= 0) {
330 run("opt_merge");
331 run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
332 }
333 run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v");
334 run("opt_expr -mux_undef");
335 run("simplemap");
336 run("ice40_ffinit");
337 run("ice40_ffssr");
338 run("ice40_opt -full");
339 }
340
341 if (check_label("map_luts"))
342 {
343 if (abc2 || help_mode) {
344 run("abc", " (only if -abc2)");
345 run("ice40_opt", "(only if -abc2)");
346 }
347 run("techmap -map +/ice40/latches_map.v");
348 if (noabc || help_mode) {
349 run("simplemap", " (only if -noabc)");
350 run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
351 }
352 if (!noabc) {
353 if (abc9) {
354 run("read_verilog -icells -lib +/ice40/abc9_model.v");
355 int wire_delay;
356 if (device_opt == "lp")
357 wire_delay = 400;
358 else if (device_opt == "u")
359 wire_delay = 750;
360 else
361 wire_delay = 250;
362 run(stringf("abc9 -W %d -lut +/ice40/abc9_%s.lut -box +/ice40/abc9_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()));
363 }
364 else
365 run("abc -dress -lut 4", "(skip if -noabc)");
366 }
367 run("ice40_wrapcarry -unwrap");
368 run("techmap -D NO_LUT -map +/ice40/cells_map.v");
369 run("clean");
370 run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
371 }
372
373 if (check_label("map_cells"))
374 {
375 if (vpr)
376 run("techmap -D NO_LUT -map +/ice40/cells_map.v");
377 else
378 run("techmap -map +/ice40/cells_map.v", "(with -D NO_LUT in vpr mode)");
379
380 run("clean");
381 }
382
383 if (check_label("check"))
384 {
385 run("autoname");
386 run("hierarchy -check");
387 run("stat");
388 run("check -noinit");
389 }
390
391 if (check_label("blif"))
392 {
393 if (!blif_file.empty() || help_mode) {
394 if (vpr || help_mode) {
395 run(stringf("opt_clean -purge"),
396 " (vpr mode)");
397 run(stringf("write_blif -attr -cname -conn -param %s",
398 help_mode ? "<file-name>" : blif_file.c_str()),
399 " (vpr mode)");
400 }
401 if (!vpr)
402 run(stringf("write_blif -gates -attr -param %s",
403 help_mode ? "<file-name>" : blif_file.c_str()),
404 " (non-vpr mode)");
405 }
406 }
407
408 if (check_label("edif"))
409 {
410 if (!edif_file.empty() || help_mode)
411 run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
412 }
413
414 if (check_label("json"))
415 {
416 if (!json_file.empty() || help_mode)
417 run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
418 }
419 }
420 } SynthIce40Pass;
421
422 PRIVATE_NAMESPACE_END