techlibs/ice40/synth_ice40.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 struct SynthIce40Pass : public ScriptPass
  29 {
  30         SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
  31
  32         void help() YS_OVERRIDE
  33         {
  34                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  35                 log("\n");
  36                 log("    synth_ice40 [options]\n");
  37                 log("\n");
  38                 log("This command runs synthesis for iCE40 FPGAs.\n");
  39                 log("\n");
  40                 log("    -top <module>\n");
  41                 log("        use the specified module as top module\n");
  42                 log("\n");
  43                 log("    -blif <file>\n");
  44                 log("        write the design to the specified BLIF file. writing of an output file\n");
  45                 log("        is omitted if this parameter is not specified.\n");
  46                 log("\n");
  47                 log("    -edif <file>\n");
  48                 log("        write the design to the specified EDIF file. writing of an output file\n");
  49                 log("        is omitted if this parameter is not specified.\n");
  50                 log("\n");
  51                 log("    -json <file>\n");
  52                 log("        write the design to the specified JSON file. writing of an output file\n");
  53                 log("        is omitted if this parameter is not specified.\n");
  54                 log("\n");
  55                 log("    -run <from_label>:<to_label>\n");
  56                 log("        only run the commands between the labels (see below). an empty\n");
  57                 log("        from label is synonymous to 'begin', and empty to label is\n");
  58                 log("        synonymous to the end of the command list.\n");
  59                 log("\n");
  60                 log("    -noflatten\n");
  61                 log("        do not flatten design before synthesis\n");
  62                 log("\n");
  63                 log("    -retime\n");
  64                 log("        run 'abc' with -dff option\n");
  65                 log("\n");
  66                 log("    -relut\n");
  67                 log("        combine LUTs after synthesis\n");
  68                 log("\n");
  69                 log("    -nocarry\n");
  70                 log("        do not use SB_CARRY cells in output netlist\n");
  71                 log("\n");
  72                 log("    -nodffe\n");
  73                 log("        do not use SB_DFFE* cells in output netlist\n");
  74                 log("\n");
  75                 log("    -dffe_min_ce_use <min_ce_use>\n");
  76                 log("        do not use SB_DFFE* cells if the resulting CE line would go to less\n");
  77                 log("        than min_ce_use SB_DFFE*in output netlist\n");
  78                 log("\n");
  79                 log("    -nobram\n");
  80                 log("        do not use SB_RAM40_4K* cells in output netlist\n");
  81                 log("\n");
  82                 log("    -abc2\n");
  83                 log("        run two passes of 'abc' for slightly improved logic density\n");
  84                 log("\n");
  85                 log("    -vpr\n");
  86                 log("        generate an output netlist (and BLIF file) suitable for VPR\n");
  87                 log("        (this feature is experimental and incomplete)\n");
  88                 log("\n");
  89                 log("\n");
  90                 log("The following commands are executed by this synthesis command:\n");
  91                 help_script();
  92                 log("\n");
  93         }
  94
  95         string top_opt, blif_file, edif_file, json_file;
  96         bool nocarry, nodffe, nobram, flatten, retime, relut, abc2, vpr;
  97         int min_ce_use;
  98
  99         void clear_flags() YS_OVERRIDE
 100         {
 101                 top_opt = "-auto-top";
 102                 blif_file = "";
 103                 edif_file = "";
 104                 json_file = "";
 105                 nocarry = false;
 106                 nodffe = false;
 107                 min_ce_use = -1;
 108                 nobram = false;
 109                 flatten = true;
 110                 retime = false;
 111                 relut = false;
 112                 abc2 = false;
 113                 vpr = false;
 114         }
 115
 116         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 117         {
 118                 string run_from, run_to;
 119                 clear_flags();
 120
 121                 size_t argidx;
 122                 for (argidx = 1; argidx < args.size(); argidx++)
 123                 {
 124                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
 125                                 top_opt = "-top " + args[++argidx];
 126                                 continue;
 127                         }
 128                         if (args[argidx] == "-blif" && argidx+1 < args.size()) {
 129                                 blif_file = args[++argidx];
 130                                 continue;
 131                         }
 132                         if (args[argidx] == "-edif" && argidx+1 < args.size()) {
 133                                 edif_file = args[++argidx];
 134                                 continue;
 135                         }
 136                         if (args[argidx] == "-json" && argidx+1 < args.size()) {
 137                                 json_file = args[++argidx];
 138                                 continue;
 139                         }
 140                         if (args[argidx] == "-run" && argidx+1 < args.size()) {
 141                                 size_t pos = args[argidx+1].find(':');
 142                                 if (pos == std::string::npos)
 143                                         break;
 144                                 run_from = args[++argidx].substr(0, pos);
 145                                 run_to = args[argidx].substr(pos+1);
 146                                 continue;
 147                         }
 148                         if (args[argidx] == "-flatten") {
 149                                 flatten = true;
 150                                 continue;
 151                         }
 152                         if (args[argidx] == "-noflatten") {
 153                                 flatten = false;
 154                                 continue;
 155                         }
 156                         if (args[argidx] == "-retime") {
 157                                 retime = true;
 158                                 continue;
 159                         }
 160                         if (args[argidx] == "-relut") {
 161                                 relut = true;
 162                                 continue;
 163                         }
 164                         if (args[argidx] == "-nocarry") {
 165                                 nocarry = true;
 166                                 continue;
 167                         }
 168                         if (args[argidx] == "-nodffe") {
 169                                 nodffe = true;
 170                                 continue;
 171                         }
 172                         if (args[argidx] == "-dffe_min_ce_use" && argidx+1 < args.size()) {
 173                                 min_ce_use = std::stoi(args[++argidx]);
 174                                 continue;
 175                         }
 176                         if (args[argidx] == "-nobram") {
 177                                 nobram = true;
 178                                 continue;
 179                         }
 180                         if (args[argidx] == "-abc2") {
 181                                 abc2 = true;
 182                                 continue;
 183                         }
 184                         if (args[argidx] == "-vpr") {
 185                                 vpr = true;
 186                                 continue;
 187                         }
 188                         break;
 189                 }
 190                 extra_args(args, argidx, design);
 191
 192                 if (!design->full_selection())
 193                         log_cmd_error("This comannd only operates on fully selected designs!\n");
 194
 195                 log_header(design, "Executing SYNTH_ICE40 pass.\n");
 196                 log_push();
 197
 198                 run_script(design, run_from, run_to);
 199
 200                 log_pop();
 201         }
 202
 203         void script() YS_OVERRIDE
 204         {
 205                 if (check_label("begin"))
 206                 {
 207                         run("read_verilog -lib +/ice40/cells_sim.v");
 208                         run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 209                 }
 210
 211                 if (flatten && check_label("flatten", "(unless -noflatten)"))
 212                 {
 213                         run("proc");
 214                         run("flatten");
 215                         run("tribuf -logic");
 216                         run("deminout");
 217                 }
 218
 219                 if (check_label("coarse"))
 220                 {
 221                         run("synth -run coarse");
 222                 }
 223
 224                 if (!nobram && check_label("bram", "(skip if -nobram)"))
 225                 {
 226                         run("memory_bram -rules +/ice40/brams.txt");
 227                         run("techmap -map +/ice40/brams_map.v");
 228                 }
 229
 230                 if (check_label("fine"))
 231                 {
 232                         run("opt -fast -mux_undef -undriven -fine");
 233                         run("memory_map");
 234                         run("opt -undriven -fine");
 235                         if (nocarry)
 236                                 run("techmap");
 237                         else
 238                                 run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
 239                         if (retime || help_mode)
 240                                 run("abc -dff", "(only if -retime)");
 241                         run("ice40_opt");
 242                 }
 243
 244                 if (check_label("map_ffs"))
 245                 {
 246                         run("dffsr2dff");
 247                         if (!nodffe)
 248                                 run("dff2dffe -direct-match $_DFF_*");
 249                         if (min_ce_use >= 0) {
 250                                 run("opt_merge");
 251                                 run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
 252                         }
 253                         run("techmap -D NO_LUT -map +/ice40/cells_map.v");
 254                         run("opt_expr -mux_undef");
 255                         run("simplemap");
 256                         run("ice40_ffinit");
 257                         run("ice40_ffssr");
 258                         run("ice40_opt -full");
 259                 }
 260
 261                 if (check_label("map_luts"))
 262                 {
 263                         if (abc2 || help_mode) {
 264                                 run("abc", "      (only if -abc2)");
 265                                 run("ice40_opt", "(only if -abc2)");
 266                         }
 267                         run("techmap -map +/ice40/latches_map.v");
 268                         run("abc -lut 4");
 269                         run("clean");
 270                         if (relut || help_mode) {
 271                                 run("ice40_unlut", "                            (only if -relut)");
 272                                 run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3", "(only if -relut)");
 273                         }
 274                 }
 275
 276                 if (check_label("map_cells"))
 277                 {
 278                         if (vpr)
 279                                 run("techmap -D NO_LUT -map +/ice40/cells_map.v");
 280                         else
 281                                 run("techmap -map +/ice40/cells_map.v", "(with -D NO_LUT in vpr mode)");
 282
 283                         run("clean");
 284                 }
 285
 286                 if (check_label("check"))
 287                 {
 288                         run("hierarchy -check");
 289                         run("stat");
 290                         run("check -noinit");
 291                 }
 292
 293                 if (check_label("blif"))
 294                 {
 295                         if (!blif_file.empty() || help_mode) {
 296                                 if (vpr || help_mode) {
 297                                         run(stringf("opt_clean -purge"),
 298                                                         "                                 (vpr mode)");
 299                                         run(stringf("write_blif -attr -cname -conn -param %s",
 300                                                         help_mode ? "<file-name>" : blif_file.c_str()),
 301                                                         " (vpr mode)");
 302                                 }
 303                                 if (!vpr)
 304                                         run(stringf("write_blif -gates -attr -param %s",
 305                                                         help_mode ? "<file-name>" : blif_file.c_str()),
 306                                                         "       (non-vpr mode)");
 307                         }
 308                 }
 309
 310                 if (check_label("edif"))
 311                 {
 312                         if (!edif_file.empty() || help_mode)
 313                                 run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
 314                 }
 315
 316                 if (check_label("json"))
 317                 {
 318                         if (!json_file.empty() || help_mode)
 319                                 run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
 320                 }
 321         }
 322 } SynthIce40Pass;
 323
 324 PRIVATE_NAMESPACE_END