Merge pull request #1761 from YosysHQ/eddie/opt_merge_speedup
[yosys.git] / techlibs / ice40 / synth_ice40.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
24
25 USING_YOSYS_NAMESPACE
26 PRIVATE_NAMESPACE_BEGIN
27
28 struct SynthIce40Pass : public ScriptPass
29 {
30 SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
31
32 void help() YS_OVERRIDE
33 {
34 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
35 log("\n");
36 log(" synth_ice40 [options]\n");
37 log("\n");
38 log("This command runs synthesis for iCE40 FPGAs.\n");
39 log("\n");
40 log(" -device < hx | lp | u >\n");
41 log(" relevant only for '-abc9' flow, optimise timing for the specified device.\n");
42 log(" default: hx\n");
43 log("\n");
44 log(" -top <module>\n");
45 log(" use the specified module as top module\n");
46 log("\n");
47 log(" -blif <file>\n");
48 log(" write the design to the specified BLIF file. writing of an output file\n");
49 log(" is omitted if this parameter is not specified.\n");
50 log("\n");
51 log(" -edif <file>\n");
52 log(" write the design to the specified EDIF file. writing of an output file\n");
53 log(" is omitted if this parameter is not specified.\n");
54 log("\n");
55 log(" -json <file>\n");
56 log(" write the design to the specified JSON file. writing of an output file\n");
57 log(" is omitted if this parameter is not specified.\n");
58 log("\n");
59 log(" -run <from_label>:<to_label>\n");
60 log(" only run the commands between the labels (see below). an empty\n");
61 log(" from label is synonymous to 'begin', and empty to label is\n");
62 log(" synonymous to the end of the command list.\n");
63 log("\n");
64 log(" -noflatten\n");
65 log(" do not flatten design before synthesis\n");
66 log("\n");
67 log(" -retime\n");
68 log(" run 'abc' with '-dff -D 1' options\n");
69 log("\n");
70 log(" -nocarry\n");
71 log(" do not use SB_CARRY cells in output netlist\n");
72 log("\n");
73 log(" -nodffe\n");
74 log(" do not use SB_DFFE* cells in output netlist\n");
75 log("\n");
76 log(" -dffe_min_ce_use <min_ce_use>\n");
77 log(" do not use SB_DFFE* cells if the resulting CE line would go to less\n");
78 log(" than min_ce_use SB_DFFE* in output netlist\n");
79 log("\n");
80 log(" -nobram\n");
81 log(" do not use SB_RAM40_4K* cells in output netlist\n");
82 log("\n");
83 log(" -dsp\n");
84 log(" use iCE40 UltraPlus DSP cells for large arithmetic\n");
85 log("\n");
86 log(" -noabc\n");
87 log(" use built-in Yosys LUT techmapping instead of abc\n");
88 log("\n");
89 log(" -abc2\n");
90 log(" run two passes of 'abc' for slightly improved logic density\n");
91 log("\n");
92 log(" -vpr\n");
93 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
94 log(" (this feature is experimental and incomplete)\n");
95 log("\n");
96 log(" -abc9\n");
97 log(" use new ABC9 flow (EXPERIMENTAL)\n");
98 log("\n");
99 log(" -flowmap\n");
100 log(" use FlowMap LUT techmapping instead of abc (EXPERIMENTAL)\n");
101 log("\n");
102 log("\n");
103 log("The following commands are executed by this synthesis command:\n");
104 help_script();
105 log("\n");
106 }
107
108 string top_opt, blif_file, edif_file, json_file, device_opt;
109 bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr, abc9, flowmap;
110 int min_ce_use;
111
112 void clear_flags() YS_OVERRIDE
113 {
114 top_opt = "-auto-top";
115 blif_file = "";
116 edif_file = "";
117 json_file = "";
118 nocarry = false;
119 nodffe = false;
120 min_ce_use = -1;
121 nobram = false;
122 dsp = false;
123 flatten = true;
124 retime = false;
125 noabc = false;
126 abc2 = false;
127 vpr = false;
128 abc9 = false;
129 flowmap = false;
130 device_opt = "hx";
131 }
132
133 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
134 {
135 string run_from, run_to;
136 clear_flags();
137
138 size_t argidx;
139 for (argidx = 1; argidx < args.size(); argidx++)
140 {
141 if (args[argidx] == "-top" && argidx+1 < args.size()) {
142 top_opt = "-top " + args[++argidx];
143 continue;
144 }
145 if (args[argidx] == "-blif" && argidx+1 < args.size()) {
146 blif_file = args[++argidx];
147 continue;
148 }
149 if (args[argidx] == "-edif" && argidx+1 < args.size()) {
150 edif_file = args[++argidx];
151 continue;
152 }
153 if (args[argidx] == "-json" && argidx+1 < args.size()) {
154 json_file = args[++argidx];
155 continue;
156 }
157 if (args[argidx] == "-run" && argidx+1 < args.size()) {
158 size_t pos = args[argidx+1].find(':');
159 if (pos == std::string::npos)
160 break;
161 run_from = args[++argidx].substr(0, pos);
162 run_to = args[argidx].substr(pos+1);
163 continue;
164 }
165 if (args[argidx] == "-flatten") {
166 flatten = true;
167 continue;
168 }
169 if (args[argidx] == "-noflatten") {
170 flatten = false;
171 continue;
172 }
173 if (args[argidx] == "-retime") {
174 retime = true;
175 continue;
176 }
177 if (args[argidx] == "-relut") {
178 // removed, opt_lut is always run
179 continue;
180 }
181 if (args[argidx] == "-nocarry") {
182 nocarry = true;
183 continue;
184 }
185 if (args[argidx] == "-nodffe") {
186 nodffe = true;
187 continue;
188 }
189 if (args[argidx] == "-dffe_min_ce_use" && argidx+1 < args.size()) {
190 min_ce_use = atoi(args[++argidx].c_str());
191 continue;
192 }
193 if (args[argidx] == "-nobram") {
194 nobram = true;
195 continue;
196 }
197 if (args[argidx] == "-dsp") {
198 dsp = true;
199 continue;
200 }
201 if (args[argidx] == "-noabc") {
202 noabc = true;
203 continue;
204 }
205 if (args[argidx] == "-abc2") {
206 abc2 = true;
207 continue;
208 }
209 if (args[argidx] == "-vpr") {
210 vpr = true;
211 continue;
212 }
213 if (args[argidx] == "-abc9") {
214 abc9 = true;
215 continue;
216 }
217 if (args[argidx] == "-device" && argidx+1 < args.size()) {
218 device_opt = args[++argidx];
219 continue;
220 }
221 if (args[argidx] == "-flowmap") {
222 flowmap = true;
223 continue;
224 }
225 break;
226 }
227 extra_args(args, argidx, design);
228
229 if (!design->full_selection())
230 log_cmd_error("This command only operates on fully selected designs!\n");
231 if (device_opt != "hx" && device_opt != "lp" && device_opt !="u")
232 log_cmd_error("Invalid or no device specified: '%s'\n", device_opt.c_str());
233
234 if (abc9 && retime)
235 log_cmd_error("-retime option not currently compatible with -abc9!\n");
236
237 if (abc9 && noabc)
238 log_cmd_error("-abc9 is incompatible with -noabc!\n");
239 if (abc9 && flowmap)
240 log_cmd_error("-abc9 is incompatible with -flowmap!\n");
241 if (flowmap && noabc)
242 log_cmd_error("-flowmap is incompatible with -noabc!\n");
243
244 log_header(design, "Executing SYNTH_ICE40 pass.\n");
245 log_push();
246
247 run_script(design, run_from, run_to);
248
249 log_pop();
250 }
251
252 void script() YS_OVERRIDE
253 {
254 std::string define;
255 if (device_opt == "lp")
256 define = "-D ICE40_LP";
257 else if (device_opt == "u")
258 define = "-D ICE40_U";
259 else
260 define = "-D ICE40_HX";
261 if (check_label("begin"))
262 {
263 run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v");
264 run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
265 run("proc");
266 }
267
268 if (check_label("flatten", "(unless -noflatten)"))
269 {
270 if (flatten) {
271 run("flatten");
272 run("tribuf -logic");
273 run("deminout");
274 }
275 }
276
277 if (check_label("coarse"))
278 {
279 run("opt_expr");
280 run("opt_clean");
281 run("check");
282 run("opt");
283 run("wreduce");
284 run("peepopt");
285 run("opt_clean");
286 run("share");
287 run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
288 run("opt_expr");
289 run("opt_clean");
290 if (help_mode || dsp) {
291 run("memory_dff"); // ice40_dsp will merge registers, reserve memory port registers first
292 run("wreduce t:$mul");
293 run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
294 "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
295 "-D DSP_NAME=$__MUL16X16", "(if -dsp)");
296 run("select a:mul2dsp", " (if -dsp)");
297 run("setattr -unset mul2dsp", " (if -dsp)");
298 run("opt_expr -fine", " (if -dsp)");
299 run("wreduce", " (if -dsp)");
300 run("select -clear", " (if -dsp)");
301 run("ice40_dsp", " (if -dsp)");
302 run("chtype -set $mul t:$__soft_mul", "(if -dsp)");
303 }
304 run("alumacc");
305 run("opt");
306 run("fsm");
307 run("opt -fast");
308 run("memory -nomap");
309 run("opt_clean");
310 }
311
312 if (!nobram && check_label("map_bram", "(skip if -nobram)"))
313 {
314 run("memory_bram -rules +/ice40/brams.txt");
315 run("techmap -map +/ice40/brams_map.v");
316 run("ice40_braminit");
317 }
318
319 if (check_label("map_ffram"))
320 {
321 run("opt -fast -mux_undef -undriven -fine");
322 run("memory_map");
323 run("opt -undriven -fine");
324 }
325
326 if (check_label("map_gates"))
327 {
328 if (nocarry)
329 run("techmap");
330 else {
331 run("ice40_wrapcarry");
332 run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
333 }
334 run("opt -fast");
335 if (retime || help_mode)
336 run("abc -dff -D 1", "(only if -retime)");
337 run("ice40_opt");
338 }
339
340 if (check_label("map_ffs"))
341 {
342 run("dffsr2dff");
343 if (!nodffe)
344 run("dff2dffe -direct-match $_DFF_*");
345 if (min_ce_use >= 0) {
346 run("opt_merge");
347 run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
348 run("simplemap t:$dff");
349 }
350 run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v");
351 run("opt_expr -mux_undef");
352 run("simplemap");
353 run("ice40_ffinit");
354 run("ice40_ffssr");
355 run("ice40_opt -full");
356 }
357
358 if (check_label("map_luts"))
359 {
360 if (abc2 || help_mode) {
361 run("abc", " (only if -abc2)");
362 run("ice40_opt", "(only if -abc2)");
363 }
364 run("techmap -map +/ice40/latches_map.v");
365 if (noabc || flowmap || help_mode) {
366 run("simplemap", " (if -noabc or -flowmap)");
367 if (noabc || help_mode)
368 run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
369 if (flowmap || help_mode)
370 run("flowmap -maxlut 4", "(only if -flowmap)");
371 }
372 if (!noabc) {
373 if (abc9) {
374 run("read_verilog " + define + " -icells -lib -specify +/abc9_model.v +/ice40/abc9_model.v");
375 int wire_delay;
376 if (device_opt == "lp")
377 wire_delay = 400;
378 else if (device_opt == "u")
379 wire_delay = 750;
380 else
381 wire_delay = 250;
382 run(stringf("abc9 -W %d", wire_delay));
383 }
384 else
385 run("abc -dress -lut 4", "(skip if -noabc)");
386 }
387 run("ice40_wrapcarry -unwrap");
388 run("techmap -D NO_LUT -map +/ice40/cells_map.v");
389 run("clean");
390 run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
391 }
392
393 if (check_label("map_cells"))
394 {
395 if (vpr)
396 run("techmap -D NO_LUT -map +/ice40/cells_map.v");
397 else
398 run("techmap -map +/ice40/cells_map.v", "(with -D NO_LUT in vpr mode)");
399
400 run("clean");
401 }
402
403 if (check_label("check"))
404 {
405 run("autoname");
406 run("hierarchy -check");
407 run("stat");
408 run("check -noinit");
409 }
410
411 if (check_label("blif"))
412 {
413 if (!blif_file.empty() || help_mode) {
414 if (vpr || help_mode) {
415 run(stringf("opt_clean -purge"),
416 " (vpr mode)");
417 run(stringf("write_blif -attr -cname -conn -param %s",
418 help_mode ? "<file-name>" : blif_file.c_str()),
419 " (vpr mode)");
420 }
421 if (!vpr)
422 run(stringf("write_blif -gates -attr -param %s",
423 help_mode ? "<file-name>" : blif_file.c_str()),
424 " (non-vpr mode)");
425 }
426 }
427
428 if (check_label("edif"))
429 {
430 if (!edif_file.empty() || help_mode)
431 run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
432 }
433
434 if (check_label("json"))
435 {
436 if (!json_file.empty() || help_mode)
437 run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
438 }
439 }
440 } SynthIce40Pass;
441
442 PRIVATE_NAMESPACE_END