2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
26 PRIVATE_NAMESPACE_BEGIN
28 struct SynthIce40Pass
: public ScriptPass
30 SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
32 void help() YS_OVERRIDE
34 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
36 log(" synth_ice40 [options]\n");
38 log("This command runs synthesis for iCE40 FPGAs.\n");
40 log(" -top <module>\n");
41 log(" use the specified module as top module\n");
43 log(" -blif <file>\n");
44 log(" write the design to the specified BLIF file. writing of an output file\n");
45 log(" is omitted if this parameter is not specified.\n");
47 log(" -edif <file>\n");
48 log(" write the design to the specified EDIF file. writing of an output file\n");
49 log(" is omitted if this parameter is not specified.\n");
51 log(" -json <file>\n");
52 log(" write the design to the specified JSON file. writing of an output file\n");
53 log(" is omitted if this parameter is not specified.\n");
55 log(" -run <from_label>:<to_label>\n");
56 log(" only run the commands between the labels (see below). an empty\n");
57 log(" from label is synonymous to 'begin', and empty to label is\n");
58 log(" synonymous to the end of the command list.\n");
61 log(" do not flatten design before synthesis\n");
64 log(" run 'abc' with -dff option\n");
67 log(" combine LUTs after synthesis\n");
70 log(" do not use SB_CARRY cells in output netlist\n");
73 log(" do not use SB_DFFE* cells in output netlist\n");
75 log(" -dffe_min_ce_use <min_ce_use>\n");
76 log(" do not use SB_DFFE* cells if the resulting CE line would go to less\n");
77 log(" than min_ce_use SB_DFFE*in output netlist\n");
80 log(" do not use SB_RAM40_4K* cells in output netlist\n");
83 log(" use iCE40 UltraPlus DSP cells for large arithmetic\n");
86 log(" use built-in Yosys LUT techmapping instead of abc\n");
89 log(" run two passes of 'abc' for slightly improved logic density\n");
92 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
93 log(" (this feature is experimental and incomplete)\n");
96 log("The following commands are executed by this synthesis command:\n");
101 string top_opt
, blif_file
, edif_file
, json_file
;
102 bool nocarry
, nodffe
, nobram
, dsp
, flatten
, retime
, relut
, noabc
, abc2
, vpr
;
105 void clear_flags() YS_OVERRIDE
107 top_opt
= "-auto-top";
124 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
126 string run_from
, run_to
;
130 for (argidx
= 1; argidx
< args
.size(); argidx
++)
132 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
133 top_opt
= "-top " + args
[++argidx
];
136 if (args
[argidx
] == "-blif" && argidx
+1 < args
.size()) {
137 blif_file
= args
[++argidx
];
140 if (args
[argidx
] == "-edif" && argidx
+1 < args
.size()) {
141 edif_file
= args
[++argidx
];
144 if (args
[argidx
] == "-json" && argidx
+1 < args
.size()) {
145 json_file
= args
[++argidx
];
148 if (args
[argidx
] == "-run" && argidx
+1 < args
.size()) {
149 size_t pos
= args
[argidx
+1].find(':');
150 if (pos
== std::string::npos
)
152 run_from
= args
[++argidx
].substr(0, pos
);
153 run_to
= args
[argidx
].substr(pos
+1);
156 if (args
[argidx
] == "-flatten") {
160 if (args
[argidx
] == "-noflatten") {
164 if (args
[argidx
] == "-retime") {
168 if (args
[argidx
] == "-relut") {
172 if (args
[argidx
] == "-nocarry") {
176 if (args
[argidx
] == "-nodffe") {
180 if (args
[argidx
] == "-dffe_min_ce_use" && argidx
+1 < args
.size()) {
181 min_ce_use
= std::stoi(args
[++argidx
]);
184 if (args
[argidx
] == "-nobram") {
188 if (args
[argidx
] == "-dsp") {
192 if (args
[argidx
] == "-noabc") {
196 if (args
[argidx
] == "-abc2") {
200 if (args
[argidx
] == "-vpr") {
206 extra_args(args
, argidx
, design
);
208 if (!design
->full_selection())
209 log_cmd_error("This command only operates on fully selected designs!\n");
211 log_header(design
, "Executing SYNTH_ICE40 pass.\n");
214 run_script(design
, run_from
, run_to
);
219 void script() YS_OVERRIDE
221 if (check_label("begin"))
223 run("read_verilog -lib +/ice40/cells_sim.v");
224 run(stringf("hierarchy -check %s", help_mode
? "-top <top>" : top_opt
.c_str()));
228 if (flatten
&& check_label("flatten", "(unless -noflatten)"))
231 run("tribuf -logic");
235 if (check_label("coarse"))
243 run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
246 if (help_mode
|| dsp
)
247 run("ice40_dsp", "(if -dsp)");
252 run("memory -nomap");
256 if (!nobram
&& check_label("bram", "(skip if -nobram)"))
258 run("memory_bram -rules +/ice40/brams.txt");
259 run("techmap -map +/ice40/brams_map.v");
260 run("ice40_braminit");
263 if (check_label("map"))
265 run("opt -fast -mux_undef -undriven -fine");
267 run("opt -undriven -fine");
270 if (check_label("map_gates"))
275 run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
276 if (retime
|| help_mode
)
277 run("abc -dff -D 1", "(only if -retime)");
281 if (check_label("map_ffs"))
285 run("dff2dffe -direct-match $_DFF_*");
286 if (min_ce_use
>= 0) {
288 run(stringf("dff2dffe -unmap-mince %d", min_ce_use
));
290 run("techmap -D NO_LUT -map +/ice40/cells_map.v");
291 run("opt_expr -mux_undef");
295 run("ice40_opt -full");
298 if (check_label("map_luts"))
300 if (abc2
|| help_mode
) {
301 run("abc", " (only if -abc2)");
302 run("ice40_opt", "(only if -abc2)");
304 run("techmap -map +/ice40/latches_map.v");
305 if (noabc
|| help_mode
) {
306 run("simplemap", " (only if -noabc)");
307 run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
310 run("abc -dress -lut 4", "(skip if -noabc)");
313 if (relut
|| help_mode
) {
314 run("ice40_unlut", " (only if -relut)");
315 run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3", "(only if -relut)");
319 if (check_label("map_cells"))
322 run("techmap -D NO_LUT -map +/ice40/cells_map.v");
324 run("techmap -map +/ice40/cells_map.v", "(with -D NO_LUT in vpr mode)");
329 if (check_label("check"))
331 run("hierarchy -check");
333 run("check -noinit");
336 if (check_label("blif"))
338 if (!blif_file
.empty() || help_mode
) {
339 if (vpr
|| help_mode
) {
340 run(stringf("opt_clean -purge"),
342 run(stringf("write_blif -attr -cname -conn -param %s",
343 help_mode
? "<file-name>" : blif_file
.c_str()),
347 run(stringf("write_blif -gates -attr -param %s",
348 help_mode
? "<file-name>" : blif_file
.c_str()),
353 if (check_label("edif"))
355 if (!edif_file
.empty() || help_mode
)
356 run(stringf("write_edif %s", help_mode
? "<file-name>" : edif_file
.c_str()));
359 if (check_label("json"))
361 if (!json_file
.empty() || help_mode
)
362 run(stringf("write_json %s", help_mode
? "<file-name>" : json_file
.c_str()));
367 PRIVATE_NAMESPACE_END