2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
26 PRIVATE_NAMESPACE_BEGIN
28 bool check_label(bool &active
, std::string run_from
, std::string run_to
, std::string label
)
30 if (label
== run_from
)
37 struct SynthIce40Pass
: public Pass
{
38 SynthIce40Pass() : Pass("synth_ice40", "synthesis for iCE40 FPGAs") { }
41 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
43 log(" synth_ice40 [options]\n");
45 log("This command runs synthesis for iCE40 FPGAs. This work is experimental.\n");
47 log(" -top <module>\n");
48 log(" use the specified module as top module (default='top')\n");
50 log(" -blif <file>\n");
51 log(" write the design to the specified BLIF file. writing of an output file\n");
52 log(" is omitted if this parameter is not specified.\n");
54 log(" -edif <file>\n");
55 log(" write the design to the specified edif file. writing of an output file\n");
56 log(" is omitted if this parameter is not specified.\n");
58 log(" -run <from_label>:<to_label>\n");
59 log(" only run the commands between the labels (see below). an empty\n");
60 log(" from label is synonymous to 'begin', and empty to label is\n");
61 log(" synonymous to the end of the command list.\n");
64 log(" do not flatten design before synthesis\n");
67 log(" run 'abc' with -dff option\n");
70 log(" do not use SB_CARRY cells in output netlist\n");
73 log(" do not use SB_RAM40_4K* cells in output netlist\n");
76 log("The following commands are executed by this synthesis command:\n");
79 log(" read_verilog -lib +/ice40/cells_sim.v\n");
80 log(" hierarchy -check -top <top>\n");
82 log(" flatten: (unless -noflatten)\n");
85 log(" tribuf -logic\n");
88 log(" synth -run coarse\n");
90 log(" bram: (skip if -nobram)\n");
91 log(" memory_bram -rules +/ice40/brams.txt\n");
92 log(" techmap -map +/ice40/brams_map.v\n");
95 log(" opt -fast -mux_undef -undriven -fine\n");
97 log(" opt -undriven -fine\n");
98 log(" techmap -map +/techmap.v [-map +/ice40/arith_map.v]\n");
99 log(" abc -dff (only if -retime)\n");
103 log(" dff2dffe -direct-match $_DFF_*\n");
104 log(" techmap -map +/ice40/cells_map.v\n");
105 log(" opt_const -mux_undef\n");
107 log(" ice40_ffinit\n");
108 log(" ice40_ffssr\n");
109 log(" ice40_opt -full\n");
112 log(" abc -lut 4\n");
115 log(" map_cells:\n");
116 log(" techmap -map +/ice40/cells_map.v\n");
120 log(" hierarchy -check\n");
122 log(" check -noinit\n");
125 log(" write_blif -gates -attr -param <file-name>\n");
128 log(" write_edif <file-name>\n");
131 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
133 std::string top_opt
= "-auto-top";
134 std::string run_from
, run_to
;
135 std::string blif_file
, edif_file
;
136 bool nocarry
= false;
142 for (argidx
= 1; argidx
< args
.size(); argidx
++)
144 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
145 top_opt
= "-top " + args
[++argidx
];
148 if (args
[argidx
] == "-blif" && argidx
+1 < args
.size()) {
149 blif_file
= args
[++argidx
];
152 if (args
[argidx
] == "-edif" && argidx
+1 < args
.size()) {
153 edif_file
= args
[++argidx
];
156 if (args
[argidx
] == "-run" && argidx
+1 < args
.size()) {
157 size_t pos
= args
[argidx
+1].find(':');
158 if (pos
== std::string::npos
)
160 run_from
= args
[++argidx
].substr(0, pos
);
161 run_to
= args
[argidx
].substr(pos
+1);
164 if (args
[argidx
] == "-flatten") {
168 if (args
[argidx
] == "-noflatten") {
172 if (args
[argidx
] == "-retime") {
176 if (args
[argidx
] == "-nocarry") {
180 if (args
[argidx
] == "-nobram") {
186 extra_args(args
, argidx
, design
);
188 if (!design
->full_selection())
189 log_cmd_error("This comannd only operates on fully selected designs!\n");
191 bool active
= run_from
.empty();
193 log_header("Executing SYNTH_ICE40 pass.\n");
196 if (check_label(active
, run_from
, run_to
, "begin"))
198 Pass::call(design
, "read_verilog -lib +/ice40/cells_sim.v");
199 Pass::call(design
, stringf("hierarchy -check %s", top_opt
.c_str()));
202 if (flatten
&& check_label(active
, run_from
, run_to
, "flatten"))
204 Pass::call(design
, "proc");
205 Pass::call(design
, "flatten");
206 Pass::call(design
, "tribuf -logic");
209 if (check_label(active
, run_from
, run_to
, "coarse"))
211 Pass::call(design
, "synth -run coarse");
214 if (!nobram
&& check_label(active
, run_from
, run_to
, "bram"))
216 Pass::call(design
, "memory_bram -rules +/ice40/brams.txt");
217 Pass::call(design
, "techmap -map +/ice40/brams_map.v");
220 if (check_label(active
, run_from
, run_to
, "fine"))
222 Pass::call(design
, "opt -fast -mux_undef -undriven -fine");
223 Pass::call(design
, "memory_map");
224 Pass::call(design
, "opt -undriven -fine");
226 Pass::call(design
, "techmap");
228 Pass::call(design
, "techmap -map +/techmap.v -map +/ice40/arith_map.v");
230 Pass::call(design
, "abc -dff");
231 Pass::call(design
, "ice40_opt");
234 if (check_label(active
, run_from
, run_to
, "map_ffs"))
236 Pass::call(design
, "dff2dffe -direct-match $_DFF_*");
237 Pass::call(design
, "techmap -map +/ice40/cells_map.v");
238 Pass::call(design
, "opt_const -mux_undef");
239 Pass::call(design
, "simplemap");
240 Pass::call(design
, "ice40_ffinit");
241 Pass::call(design
, "ice40_ffssr");
242 Pass::call(design
, "ice40_opt -full");
245 if (check_label(active
, run_from
, run_to
, "map_luts"))
247 Pass::call(design
, "abc -lut 4");
248 Pass::call(design
, "clean");
251 if (check_label(active
, run_from
, run_to
, "map_cells"))
253 Pass::call(design
, "techmap -map +/ice40/cells_map.v");
254 Pass::call(design
, "clean");
257 if (check_label(active
, run_from
, run_to
, "check"))
259 Pass::call(design
, "hierarchy -check");
260 Pass::call(design
, "stat");
261 Pass::call(design
, "check -noinit");
264 if (check_label(active
, run_from
, run_to
, "blif"))
266 if (!blif_file
.empty())
267 Pass::call(design
, stringf("write_blif -gates -attr -param %s", blif_file
.c_str()));
270 if (check_label(active
, run_from
, run_to
, "edif"))
272 if (!edif_file
.empty())
273 Pass::call(design
, stringf("write_edif %s", edif_file
.c_str()));
280 PRIVATE_NAMESPACE_END