2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
26 PRIVATE_NAMESPACE_BEGIN
28 struct SynthIce40Pass
: public ScriptPass
30 SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
32 void help() YS_OVERRIDE
34 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
36 log(" synth_ice40 [options]\n");
38 log("This command runs synthesis for iCE40 FPGAs.\n");
40 log(" -device < hx | lp | u >\n");
41 log(" relevant only for '-abc9' flow, optimise timing for the specified device.\n");
42 log(" default: hx\n");
44 log(" -top <module>\n");
45 log(" use the specified module as top module\n");
47 log(" -blif <file>\n");
48 log(" write the design to the specified BLIF file. writing of an output file\n");
49 log(" is omitted if this parameter is not specified.\n");
51 log(" -edif <file>\n");
52 log(" write the design to the specified EDIF file. writing of an output file\n");
53 log(" is omitted if this parameter is not specified.\n");
55 log(" -json <file>\n");
56 log(" write the design to the specified JSON file. writing of an output file\n");
57 log(" is omitted if this parameter is not specified.\n");
59 log(" -run <from_label>:<to_label>\n");
60 log(" only run the commands between the labels (see below). an empty\n");
61 log(" from label is synonymous to 'begin', and empty to label is\n");
62 log(" synonymous to the end of the command list.\n");
65 log(" do not flatten design before synthesis\n");
68 log(" run 'abc' with '-dff -D 1' options\n");
71 log(" do not use SB_CARRY cells in output netlist\n");
74 log(" do not use SB_DFFE* cells in output netlist\n");
76 log(" -dffe_min_ce_use <min_ce_use>\n");
77 log(" do not use SB_DFFE* cells if the resulting CE line would go to less\n");
78 log(" than min_ce_use SB_DFFE* in output netlist\n");
81 log(" do not use SB_RAM40_4K* cells in output netlist\n");
84 log(" use iCE40 UltraPlus DSP cells for large arithmetic\n");
87 log(" use built-in Yosys LUT techmapping instead of abc\n");
90 log(" run two passes of 'abc' for slightly improved logic density\n");
93 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
94 log(" (this feature is experimental and incomplete)\n");
97 log(" use new ABC9 flow (EXPERIMENTAL)\n");
100 log("The following commands are executed by this synthesis command:\n");
105 string top_opt
, blif_file
, edif_file
, json_file
, abc
, device_opt
;
106 bool nocarry
, nodffe
, nobram
, dsp
, flatten
, retime
, noabc
, abc2
, vpr
;
109 void clear_flags() YS_OVERRIDE
111 top_opt
= "-auto-top";
129 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
131 string run_from
, run_to
;
135 for (argidx
= 1; argidx
< args
.size(); argidx
++)
137 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
138 top_opt
= "-top " + args
[++argidx
];
141 if (args
[argidx
] == "-blif" && argidx
+1 < args
.size()) {
142 blif_file
= args
[++argidx
];
145 if (args
[argidx
] == "-edif" && argidx
+1 < args
.size()) {
146 edif_file
= args
[++argidx
];
149 if (args
[argidx
] == "-json" && argidx
+1 < args
.size()) {
150 json_file
= args
[++argidx
];
153 if (args
[argidx
] == "-run" && argidx
+1 < args
.size()) {
154 size_t pos
= args
[argidx
+1].find(':');
155 if (pos
== std::string::npos
)
157 run_from
= args
[++argidx
].substr(0, pos
);
158 run_to
= args
[argidx
].substr(pos
+1);
161 if (args
[argidx
] == "-flatten") {
165 if (args
[argidx
] == "-noflatten") {
169 if (args
[argidx
] == "-retime") {
173 if (args
[argidx
] == "-relut") {
174 // removed, opt_lut is always run
177 if (args
[argidx
] == "-nocarry") {
181 if (args
[argidx
] == "-nodffe") {
185 if (args
[argidx
] == "-dffe_min_ce_use" && argidx
+1 < args
.size()) {
186 min_ce_use
= atoi(args
[++argidx
].c_str());
189 if (args
[argidx
] == "-nobram") {
193 if (args
[argidx
] == "-dsp") {
197 if (args
[argidx
] == "-noabc") {
201 if (args
[argidx
] == "-abc2") {
205 if (args
[argidx
] == "-vpr") {
209 if (args
[argidx
] == "-abc9") {
213 if (args
[argidx
] == "-device" && argidx
+1 < args
.size()) {
214 device_opt
= args
[++argidx
];
219 extra_args(args
, argidx
, design
);
221 if (!design
->full_selection())
222 log_cmd_error("This command only operates on fully selected designs!\n");
223 if (device_opt
!= "hx" && device_opt
!= "lp" && device_opt
!="u")
224 log_cmd_error("Invalid or no device specified: '%s'\n", device_opt
.c_str());
226 if (abc
== "abc9" && retime
)
227 log_cmd_error("-retime option not currently compatible with -abc9!\n");
229 log_header(design
, "Executing SYNTH_ICE40 pass.\n");
232 run_script(design
, run_from
, run_to
);
237 void script() YS_OVERRIDE
239 if (check_label("begin"))
242 if (device_opt
== "lp")
243 define
= "-D ICE40_LP";
244 else if (device_opt
== "u")
245 define
= "-D ICE40_U";
247 define
= "-D ICE40_HX";
248 run("read_verilog " + define
+ " -lib +/ice40/cells_sim.v");
249 run(stringf("hierarchy -check %s", help_mode
? "-top <top>" : top_opt
.c_str()));
253 if (check_label("flatten", "(unless -noflatten)"))
257 run("tribuf -logic");
262 if (check_label("coarse"))
272 run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
275 if (help_mode
|| dsp
) {
277 run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
278 "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
279 "-D DSP_NAME=$__MUL16X16", "(if -dsp)");
280 run("select a:mul2dsp", " (if -dsp)");
281 run("setattr -unset mul2dsp", " (if -dsp)");
282 run("opt_expr -fine", " (if -dsp)");
283 run("wreduce", " (if -dsp)");
284 run("select -clear", " (if -dsp)");
285 run("ice40_dsp", " (if -dsp)");
286 run("chtype -set $mul t:$__soft_mul", "(if -dsp)");
292 run("memory -nomap");
296 if (!nobram
&& check_label("map_bram", "(skip if -nobram)"))
298 run("memory_bram -rules +/ice40/brams.txt");
299 run("techmap -map +/ice40/brams_map.v");
300 run("ice40_braminit");
303 if (check_label("map_ffram"))
305 run("opt -fast -mux_undef -undriven -fine");
307 run("opt -undriven -fine");
310 if (check_label("map_gates"))
315 run("ice40_wrapcarry");
316 run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
318 if (retime
|| help_mode
)
319 run(abc
+ " -dff -D 1", "(only if -retime)");
323 if (check_label("map_ffs"))
327 run("dff2dffe -direct-match $_DFF_*");
328 if (min_ce_use
>= 0) {
330 run(stringf("dff2dffe -unmap-mince %d", min_ce_use
));
332 run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v");
333 run("opt_expr -mux_undef");
337 run("ice40_opt -full");
340 if (check_label("map_luts"))
342 if (abc2
|| help_mode
) {
343 run(abc
, " (only if -abc2)");
344 run("ice40_opt", "(only if -abc2)");
346 run("techmap -map +/ice40/latches_map.v");
347 if (noabc
|| help_mode
) {
348 run("simplemap", " (only if -noabc)");
349 run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
353 run("read_verilog -icells -lib +/ice40/abc9_model.v");
355 if (device_opt
== "lp")
357 else if (device_opt
== "u")
361 run(abc
+ stringf(" -W %d -lut +/ice40/abc9_%s.lut -box +/ice40/abc9_%s.box", wire_delay
, device_opt
.c_str(), device_opt
.c_str()), "(skip if -noabc)");
364 run(abc
+ " -dress -lut 4", "(skip if -noabc)");
366 run("ice40_wrapcarry -unwrap");
367 run("techmap -D NO_LUT -map +/ice40/cells_map.v");
369 run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
372 if (check_label("map_cells"))
375 run("techmap -D NO_LUT -map +/ice40/cells_map.v");
377 run("techmap -map +/ice40/cells_map.v", "(with -D NO_LUT in vpr mode)");
382 if (check_label("check"))
385 run("hierarchy -check");
387 run("check -noinit");
390 if (check_label("blif"))
392 if (!blif_file
.empty() || help_mode
) {
393 if (vpr
|| help_mode
) {
394 run(stringf("opt_clean -purge"),
396 run(stringf("write_blif -attr -cname -conn -param %s",
397 help_mode
? "<file-name>" : blif_file
.c_str()),
401 run(stringf("write_blif -gates -attr -param %s",
402 help_mode
? "<file-name>" : blif_file
.c_str()),
407 if (check_label("edif"))
409 if (!edif_file
.empty() || help_mode
)
410 run(stringf("write_edif %s", help_mode
? "<file-name>" : edif_file
.c_str()));
413 if (check_label("json"))
415 if (!json_file
.empty() || help_mode
)
416 run(stringf("write_json %s", help_mode
? "<file-name>" : json_file
.c_str()));
421 PRIVATE_NAMESPACE_END