techlibs/ice40/synth_ice40.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 struct SynthIce40Pass : public ScriptPass
  29 {
  30         SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
  31
  32         virtual void help() YS_OVERRIDE
  33         {
  34                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  35                 log("\n");
  36                 log("    synth_ice40 [options]\n");
  37                 log("\n");
  38                 log("This command runs synthesis for iCE40 FPGAs.\n");
  39                 log("\n");
  40                 log("    -top <module>\n");
  41                 log("        use the specified module as top module\n");
  42                 log("\n");
  43                 log("    -blif <file>\n");
  44                 log("        write the design to the specified BLIF file. writing of an output file\n");
  45                 log("        is omitted if this parameter is not specified.\n");
  46                 log("\n");
  47                 log("    -edif <file>\n");
  48                 log("        write the design to the specified edif file. writing of an output file\n");
  49                 log("        is omitted if this parameter is not specified.\n");
  50                 log("\n");
  51                 log("    -run <from_label>:<to_label>\n");
  52                 log("        only run the commands between the labels (see below). an empty\n");
  53                 log("        from label is synonymous to 'begin', and empty to label is\n");
  54                 log("        synonymous to the end of the command list.\n");
  55                 log("\n");
  56                 log("    -noflatten\n");
  57                 log("        do not flatten design before synthesis\n");
  58                 log("\n");
  59                 log("    -retime\n");
  60                 log("        run 'abc' with -dff option\n");
  61                 log("\n");
  62                 log("    -nocarry\n");
  63                 log("        do not use SB_CARRY cells in output netlist\n");
  64                 log("\n");
  65                 log("    -nobram\n");
  66                 log("        do not use SB_RAM40_4K* cells in output netlist\n");
  67                 log("\n");
  68                 log("    -abc2\n");
  69                 log("        run two passes of 'abc' for slightly improved logic density\n");
  70                 log("\n");
  71                 log("    -vpr\n");
  72                 log("        generate an output netlist (and BLIF file) suitable for VPR\n");
  73                 log("        (this fueature is experimental and incomplete)\n");
  74                 log("\n");
  75                 log("\n");
  76                 log("The following commands are executed by this synthesis command:\n");
  77                 help_script();
  78                 log("\n");
  79         }
  80
  81         string top_opt, blif_file, edif_file;
  82         bool nocarry, nobram, flatten, retime, abc2, vpr;
  83
  84         virtual void clear_flags() YS_OVERRIDE
  85         {
  86                 top_opt = "-auto-top";
  87                 blif_file = "";
  88                 edif_file = "";
  89                 nocarry = false;
  90                 nobram = false;
  91                 flatten = true;
  92                 retime = false;
  93                 abc2 = false;
  94                 vpr = false;
  95         }
  96
  97         virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
  98         {
  99                 string run_from, run_to;
 100                 clear_flags();
 101
 102                 size_t argidx;
 103                 for (argidx = 1; argidx < args.size(); argidx++)
 104                 {
 105                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
 106                                 top_opt = "-top " + args[++argidx];
 107                                 continue;
 108                         }
 109                         if (args[argidx] == "-blif" && argidx+1 < args.size()) {
 110                                 blif_file = args[++argidx];
 111                                 continue;
 112                         }
 113                         if (args[argidx] == "-edif" && argidx+1 < args.size()) {
 114                                 edif_file = args[++argidx];
 115                                 continue;
 116                         }
 117                         if (args[argidx] == "-run" && argidx+1 < args.size()) {
 118                                 size_t pos = args[argidx+1].find(':');
 119                                 if (pos == std::string::npos)
 120                                         break;
 121                                 run_from = args[++argidx].substr(0, pos);
 122                                 run_to = args[argidx].substr(pos+1);
 123                                 continue;
 124                         }
 125                         if (args[argidx] == "-flatten") {
 126                                 flatten = true;
 127                                 continue;
 128                         }
 129                         if (args[argidx] == "-noflatten") {
 130                                 flatten = false;
 131                                 continue;
 132                         }
 133                         if (args[argidx] == "-retime") {
 134                                 retime = true;
 135                                 continue;
 136                         }
 137                         if (args[argidx] == "-nocarry") {
 138                                 nocarry = true;
 139                                 continue;
 140                         }
 141                         if (args[argidx] == "-nobram") {
 142                                 nobram = true;
 143                                 continue;
 144                         }
 145                         if (args[argidx] == "-abc2") {
 146                                 abc2 = true;
 147                                 continue;
 148                         }
 149                         if (args[argidx] == "-vpr") {
 150                                 vpr = true;
 151                                 continue;
 152                         }
 153                         break;
 154                 }
 155                 extra_args(args, argidx, design);
 156
 157                 if (!design->full_selection())
 158                         log_cmd_error("This comannd only operates on fully selected designs!\n");
 159
 160                 log_header(design, "Executing SYNTH_ICE40 pass.\n");
 161                 log_push();
 162
 163                 run_script(design, run_from, run_to);
 164
 165                 log_pop();
 166         }
 167
 168         virtual void script() YS_OVERRIDE
 169         {
 170                 if (check_label("begin"))
 171                 {
 172                         run("read_verilog -lib +/ice40/cells_sim.v");
 173                         run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 174                 }
 175
 176                 if (flatten && check_label("flatten", "(unless -noflatten)"))
 177                 {
 178                         run("proc");
 179                         run("flatten");
 180                         run("tribuf -logic");
 181                         run("deminout");
 182                 }
 183
 184                 if (check_label("coarse"))
 185                 {
 186                         run("synth -run coarse");
 187                 }
 188
 189                 if (!nobram && check_label("bram", "(skip if -nobram)"))
 190                 {
 191                         run("memory_bram -rules +/ice40/brams.txt");
 192                         run("techmap -map +/ice40/brams_map.v");
 193                 }
 194
 195                 if (check_label("fine"))
 196                 {
 197                         run("opt -fast -mux_undef -undriven -fine");
 198                         run("memory_map");
 199                         run("opt -undriven -fine");
 200                         if (nocarry)
 201                                 run("techmap");
 202                         else
 203                                 run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
 204                         if (retime || help_mode)
 205                                 run("abc -dff", "(only if -retime)");
 206                         run("ice40_opt");
 207                 }
 208
 209                 if (check_label("map_ffs"))
 210                 {
 211                         run("dffsr2dff");
 212                         run("dff2dffe -direct-match $_DFF_*");
 213                         run("techmap -D NO_SB_LUT4 -map +/ice40/cells_map.v");
 214                         run("opt_expr -mux_undef");
 215                         run("simplemap");
 216                         run("ice40_ffinit");
 217                         run("ice40_ffssr");
 218                         run("ice40_opt -full");
 219                 }
 220
 221                 if (check_label("map_luts"))
 222                 {
 223                         if (abc2 || help_mode) {
 224                                 run("abc", "      (only if -abc2)");
 225                                 run("ice40_opt", "(only if -abc2)");
 226                         }
 227                         run("techmap -map +/ice40/latches_map.v");
 228                         run("abc -lut 4");
 229                         run("clean");
 230                 }
 231
 232                 if (check_label("map_cells"))
 233                 {
 234                         if (vpr)
 235                                 run("techmap -D NO_SB_LUT4 -map +/ice40/cells_map.v");
 236                         else
 237                                 run("techmap -map +/ice40/cells_map.v", "(with -D NO_SB_LUT4 in vpr mode)");
 238
 239                         run("clean");
 240                 }
 241
 242                 if (check_label("check"))
 243                 {
 244                         run("hierarchy -check");
 245                         run("stat");
 246                         run("check -noinit");
 247                 }
 248
 249                 if (check_label("blif"))
 250                 {
 251                         if (!blif_file.empty() || help_mode) {
 252                                 if (vpr || help_mode) {
 253                                         run(stringf("opt_clean -purge"),
 254                                                         "                          (vpr mode)");
 255                                         run(stringf("write_blif %s", help_mode ? "<file-name>" : blif_file.c_str()),
 256                                                         "                    (vpr mode)");
 257                                 }
 258                                 if (!vpr)
 259                                         run(stringf("write_blif -gates -attr -param %s",
 260                                                         help_mode ? "<file-name>" : blif_file.c_str()), "(non-vpr mode)");
 261                         }
 262                 }
 263
 264                 if (check_label("edif"))
 265                 {
 266                         if (!edif_file.empty() || help_mode)
 267                                 run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
 268                 }
 269         }
 270 } SynthIce40Pass;
 271
 272 PRIVATE_NAMESPACE_END