techlibs/ice40/synth_ice40.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 struct SynthIce40Pass : public ScriptPass
  29 {
  30         SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
  31
  32         void help() YS_OVERRIDE
  33         {
  34                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  35                 log("\n");
  36                 log("    synth_ice40 [options]\n");
  37                 log("\n");
  38                 log("This command runs synthesis for iCE40 FPGAs.\n");
  39                 log("\n");
  40                 log("    -top <module>\n");
  41                 log("        use the specified module as top module\n");
  42                 log("\n");
  43                 log("    -blif <file>\n");
  44                 log("        write the design to the specified BLIF file. writing of an output file\n");
  45                 log("        is omitted if this parameter is not specified.\n");
  46                 log("\n");
  47                 log("    -edif <file>\n");
  48                 log("        write the design to the specified EDIF file. writing of an output file\n");
  49                 log("        is omitted if this parameter is not specified.\n");
  50                 log("\n");
  51                 log("    -json <file>\n");
  52                 log("        write the design to the specified JSON file. writing of an output file\n");
  53                 log("        is omitted if this parameter is not specified.\n");
  54                 log("\n");
  55                 log("    -run <from_label>:<to_label>\n");
  56                 log("        only run the commands between the labels (see below). an empty\n");
  57                 log("        from label is synonymous to 'begin', and empty to label is\n");
  58                 log("        synonymous to the end of the command list.\n");
  59                 log("\n");
  60                 log("    -noflatten\n");
  61                 log("        do not flatten design before synthesis\n");
  62                 log("\n");
  63                 log("    -retime\n");
  64                 log("        run 'abc' with -dff option\n");
  65                 log("\n");
  66                 log("    -nocarry\n");
  67                 log("        do not use SB_CARRY cells in output netlist\n");
  68                 log("\n");
  69                 log("    -nodffe\n");
  70                 log("        do not use SB_DFFE* cells in output netlist\n");
  71                 log("\n");
  72                 log("    -nobram\n");
  73                 log("        do not use SB_RAM40_4K* cells in output netlist\n");
  74                 log("\n");
  75                 log("    -abc2\n");
  76                 log("        run two passes of 'abc' for slightly improved logic density\n");
  77                 log("\n");
  78                 log("    -vpr\n");
  79                 log("        generate an output netlist (and BLIF file) suitable for VPR\n");
  80                 log("        (this feature is experimental and incomplete)\n");
  81                 log("\n");
  82                 log("\n");
  83                 log("The following commands are executed by this synthesis command:\n");
  84                 help_script();
  85                 log("\n");
  86         }
  87
  88         string top_opt, blif_file, edif_file, json_file;
  89         bool nocarry, nodffe, nobram, flatten, retime, abc2, vpr;
  90
  91         void clear_flags() YS_OVERRIDE
  92         {
  93                 top_opt = "-auto-top";
  94                 blif_file = "";
  95                 edif_file = "";
  96                 json_file = "";
  97                 nocarry = false;
  98                 nodffe = false;
  99                 nobram = false;
 100                 flatten = true;
 101                 retime = false;
 102                 abc2 = false;
 103                 vpr = false;
 104         }
 105
 106         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 107         {
 108                 string run_from, run_to;
 109                 clear_flags();
 110
 111                 size_t argidx;
 112                 for (argidx = 1; argidx < args.size(); argidx++)
 113                 {
 114                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
 115                                 top_opt = "-top " + args[++argidx];
 116                                 continue;
 117                         }
 118                         if (args[argidx] == "-blif" && argidx+1 < args.size()) {
 119                                 blif_file = args[++argidx];
 120                                 continue;
 121                         }
 122                         if (args[argidx] == "-edif" && argidx+1 < args.size()) {
 123                                 edif_file = args[++argidx];
 124                                 continue;
 125                         }
 126                         if (args[argidx] == "-json" && argidx+1 < args.size()) {
 127                                 json_file = args[++argidx];
 128                                 continue;
 129                         }
 130                         if (args[argidx] == "-run" && argidx+1 < args.size()) {
 131                                 size_t pos = args[argidx+1].find(':');
 132                                 if (pos == std::string::npos)
 133                                         break;
 134                                 run_from = args[++argidx].substr(0, pos);
 135                                 run_to = args[argidx].substr(pos+1);
 136                                 continue;
 137                         }
 138                         if (args[argidx] == "-flatten") {
 139                                 flatten = true;
 140                                 continue;
 141                         }
 142                         if (args[argidx] == "-noflatten") {
 143                                 flatten = false;
 144                                 continue;
 145                         }
 146                         if (args[argidx] == "-retime") {
 147                                 retime = true;
 148                                 continue;
 149                         }
 150                         if (args[argidx] == "-nocarry") {
 151                                 nocarry = true;
 152                                 continue;
 153                         }
 154                         if (args[argidx] == "-nodffe") {
 155                                 nodffe = true;
 156                                 continue;
 157                         }
 158                         if (args[argidx] == "-nobram") {
 159                                 nobram = true;
 160                                 continue;
 161                         }
 162                         if (args[argidx] == "-abc2") {
 163                                 abc2 = true;
 164                                 continue;
 165                         }
 166                         if (args[argidx] == "-vpr") {
 167                                 vpr = true;
 168                                 continue;
 169                         }
 170                         break;
 171                 }
 172                 extra_args(args, argidx, design);
 173
 174                 if (!design->full_selection())
 175                         log_cmd_error("This comannd only operates on fully selected designs!\n");
 176
 177                 log_header(design, "Executing SYNTH_ICE40 pass.\n");
 178                 log_push();
 179
 180                 run_script(design, run_from, run_to);
 181
 182                 log_pop();
 183         }
 184
 185         void script() YS_OVERRIDE
 186         {
 187                 if (check_label("begin"))
 188                 {
 189                         run("read_verilog -lib +/ice40/cells_sim.v");
 190                         run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 191                 }
 192
 193                 if (flatten && check_label("flatten", "(unless -noflatten)"))
 194                 {
 195                         run("proc");
 196                         run("flatten");
 197                         run("tribuf -logic");
 198                         run("deminout");
 199                 }
 200
 201                 if (check_label("coarse"))
 202                 {
 203                         run("synth -run coarse");
 204                 }
 205
 206                 if (!nobram && check_label("bram", "(skip if -nobram)"))
 207                 {
 208                         run("memory_bram -rules +/ice40/brams.txt");
 209                         run("techmap -map +/ice40/brams_map.v");
 210                 }
 211
 212                 if (check_label("fine"))
 213                 {
 214                         run("opt -fast -mux_undef -undriven -fine");
 215                         run("memory_map");
 216                         run("opt -undriven -fine");
 217                         if (nocarry)
 218                                 run("techmap");
 219                         else
 220                                 run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
 221                         if (retime || help_mode)
 222                                 run("abc -dff", "(only if -retime)");
 223                         run("ice40_opt");
 224                 }
 225
 226                 if (check_label("map_ffs"))
 227                 {
 228                         run("dffsr2dff");
 229                         if (!nodffe)
 230                                 run("dff2dffe -direct-match $_DFF_*");
 231                         run("techmap -D NO_LUT -map +/ice40/cells_map.v");
 232                         run("opt_expr -mux_undef");
 233                         run("simplemap");
 234                         run("ice40_ffinit");
 235                         run("ice40_ffssr");
 236                         run("ice40_opt -full");
 237                 }
 238
 239                 if (check_label("map_luts"))
 240                 {
 241                         if (abc2 || help_mode) {
 242                                 run("abc", "      (only if -abc2)");
 243                                 run("ice40_opt", "(only if -abc2)");
 244                         }
 245                         run("techmap -map +/ice40/latches_map.v");
 246                         run("abc -lut 4");
 247                         run("clean");
 248                 }
 249
 250                 if (check_label("map_cells"))
 251                 {
 252                         if (vpr)
 253                                 run("techmap -D NO_LUT -map +/ice40/cells_map.v");
 254                         else
 255                                 run("techmap -map +/ice40/cells_map.v", "(with -D NO_LUT in vpr mode)");
 256
 257                         run("clean");
 258                 }
 259
 260                 if (check_label("check"))
 261                 {
 262                         run("hierarchy -check");
 263                         run("stat");
 264                         run("check -noinit");
 265                 }
 266
 267                 if (check_label("blif"))
 268                 {
 269                         if (!blif_file.empty() || help_mode) {
 270                                 if (vpr || help_mode) {
 271                                         run(stringf("opt_clean -purge"),
 272                                                         "                                 (vpr mode)");
 273                                         run(stringf("write_blif -attr -cname -conn -param %s",
 274                                                         help_mode ? "<file-name>" : blif_file.c_str()),
 275                                                         " (vpr mode)");
 276                                 }
 277                                 if (!vpr)
 278                                         run(stringf("write_blif -gates -attr -param %s",
 279                                                         help_mode ? "<file-name>" : blif_file.c_str()),
 280                                                         "       (non-vpr mode)");
 281                         }
 282                 }
 283
 284                 if (check_label("edif"))
 285                 {
 286                         if (!edif_file.empty() || help_mode)
 287                                 run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
 288                 }
 289
 290                 if (check_label("json"))
 291                 {
 292                         if (!json_file.empty() || help_mode)
 293                                 run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
 294                 }
 295         }
 296 } SynthIce40Pass;
 297
 298 PRIVATE_NAMESPACE_END