techlibs/ice40/synth_ice40.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 struct SynthIce40Pass : public ScriptPass
  29 {
  30         SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
  31
  32         virtual void help() YS_OVERRIDE
  33         {
  34                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  35                 log("\n");
  36                 log("    synth_ice40 [options]\n");
  37                 log("\n");
  38                 log("This command runs synthesis for iCE40 FPGAs.\n");
  39                 log("\n");
  40                 log("    -top <module>\n");
  41                 log("        use the specified module as top module\n");
  42                 log("\n");
  43                 log("    -blif <file>\n");
  44                 log("        write the design to the specified BLIF file. writing of an output file\n");
  45                 log("        is omitted if this parameter is not specified.\n");
  46                 log("\n");
  47                 log("    -edif <file>\n");
  48                 log("        write the design to the specified edif file. writing of an output file\n");
  49                 log("        is omitted if this parameter is not specified.\n");
  50                 log("\n");
  51                 log("    -run <from_label>:<to_label>\n");
  52                 log("        only run the commands between the labels (see below). an empty\n");
  53                 log("        from label is synonymous to 'begin', and empty to label is\n");
  54                 log("        synonymous to the end of the command list.\n");
  55                 log("\n");
  56                 log("    -noflatten\n");
  57                 log("        do not flatten design before synthesis\n");
  58                 log("\n");
  59                 log("    -retime\n");
  60                 log("        run 'abc' with -dff option\n");
  61                 log("\n");
  62                 log("    -nocarry\n");
  63                 log("        do not use SB_CARRY cells in output netlist\n");
  64                 log("\n");
  65                 log("    -nobram\n");
  66                 log("        do not use SB_RAM40_4K* cells in output netlist\n");
  67                 log("\n");
  68                 log("    -abc2\n");
  69                 log("        run two passes of 'abc' for slightly improved logic density\n");
  70                 log("\n");
  71                 log("\n");
  72                 log("The following commands are executed by this synthesis command:\n");
  73                 help_script();
  74                 log("\n");
  75         }
  76
  77         string top_opt, blif_file, edif_file;
  78         bool nocarry, nobram, flatten, retime, abc2;
  79
  80         virtual void clear_flags() YS_OVERRIDE
  81         {
  82                 top_opt = "-auto-top";
  83                 blif_file = "";
  84                 edif_file = "";
  85                 nocarry = false;
  86                 nobram = false;
  87                 flatten = true;
  88                 retime = false;
  89                 abc2 = false;
  90         }
  91
  92         virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
  93         {
  94                 string run_from, run_to;
  95                 clear_flags();
  96
  97                 size_t argidx;
  98                 for (argidx = 1; argidx < args.size(); argidx++)
  99                 {
 100                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
 101                                 top_opt = "-top " + args[++argidx];
 102                                 continue;
 103                         }
 104                         if (args[argidx] == "-blif" && argidx+1 < args.size()) {
 105                                 blif_file = args[++argidx];
 106                                 continue;
 107                         }
 108                         if (args[argidx] == "-edif" && argidx+1 < args.size()) {
 109                                 edif_file = args[++argidx];
 110                                 continue;
 111                         }
 112                         if (args[argidx] == "-run" && argidx+1 < args.size()) {
 113                                 size_t pos = args[argidx+1].find(':');
 114                                 if (pos == std::string::npos)
 115                                         break;
 116                                 run_from = args[++argidx].substr(0, pos);
 117                                 run_to = args[argidx].substr(pos+1);
 118                                 continue;
 119                         }
 120                         if (args[argidx] == "-flatten") {
 121                                 flatten = true;
 122                                 continue;
 123                         }
 124                         if (args[argidx] == "-noflatten") {
 125                                 flatten = false;
 126                                 continue;
 127                         }
 128                         if (args[argidx] == "-retime") {
 129                                 retime = true;
 130                                 continue;
 131                         }
 132                         if (args[argidx] == "-nocarry") {
 133                                 nocarry = true;
 134                                 continue;
 135                         }
 136                         if (args[argidx] == "-nobram") {
 137                                 nobram = true;
 138                                 continue;
 139                         }
 140                         if (args[argidx] == "-abc2") {
 141                                 abc2 = true;
 142                                 continue;
 143                         }
 144                         break;
 145                 }
 146                 extra_args(args, argidx, design);
 147
 148                 if (!design->full_selection())
 149                         log_cmd_error("This comannd only operates on fully selected designs!\n");
 150
 151                 log_header(design, "Executing SYNTH_ICE40 pass.\n");
 152                 log_push();
 153
 154                 run_script(design, run_from, run_to);
 155
 156                 log_pop();
 157         }
 158
 159         virtual void script() YS_OVERRIDE
 160         {
 161                 if (check_label("begin"))
 162                 {
 163                         run("read_verilog -lib +/ice40/cells_sim.v");
 164                         run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 165                 }
 166
 167                 if (flatten && check_label("flatten", "(unless -noflatten)"))
 168                 {
 169                         run("proc");
 170                         run("flatten");
 171                         run("tribuf -logic");
 172                         run("deminout");
 173                 }
 174
 175                 if (check_label("coarse"))
 176                 {
 177                         run("synth -run coarse");
 178                 }
 179
 180                 if (!nobram && check_label("bram", "(skip if -nobram)"))
 181                 {
 182                         run("memory_bram -rules +/ice40/brams.txt");
 183                         run("techmap -map +/ice40/brams_map.v");
 184                 }
 185
 186                 if (check_label("fine"))
 187                 {
 188                         run("opt -fast -mux_undef -undriven -fine");
 189                         run("memory_map");
 190                         run("opt -undriven -fine");
 191                         if (nocarry)
 192                                 run("techmap");
 193                         else
 194                                 run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
 195                         if (retime || help_mode)
 196                                 run("abc -dff", "(only if -retime)");
 197                         run("ice40_opt");
 198                 }
 199
 200                 if (check_label("map_ffs"))
 201                 {
 202                         run("dffsr2dff");
 203                         run("dff2dffe -direct-match $_DFF_*");
 204                         run("techmap -map +/ice40/cells_map.v");
 205                         run("opt_expr -mux_undef");
 206                         run("simplemap");
 207                         run("ice40_ffinit");
 208                         run("ice40_ffssr");
 209                         run("ice40_opt -full");
 210                 }
 211
 212                 if (check_label("map_luts"))
 213                 {
 214                         if (abc2 || help_mode) {
 215                                 run("abc", "      (only if -abc2)");
 216                                 run("ice40_opt", "(only if -abc2)");
 217                         }
 218                         run("techmap -map +/ice40/latches_map.v");
 219                         run("abc -lut 4");
 220                         run("clean");
 221                 }
 222
 223                 if (check_label("map_cells"))
 224                 {
 225                         run("techmap -map +/ice40/cells_map.v");
 226                         run("clean");
 227                 }
 228
 229                 if (check_label("check"))
 230                 {
 231                         run("hierarchy -check");
 232                         run("stat");
 233                         run("check -noinit");
 234                 }
 235
 236                 if (check_label("blif"))
 237                 {
 238                         if (!blif_file.empty() || help_mode)
 239                                 run(stringf("write_blif -gates -attr -param %s", help_mode ? "<file-name>" : blif_file.c_str()));
 240                 }
 241
 242                 if (check_label("edif"))
 243                 {
 244                         if (!edif_file.empty() || help_mode)
 245                                 run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
 246                 }
 247         }
 248 } SynthIce40Pass;
 249
 250 PRIVATE_NAMESPACE_END