2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
26 PRIVATE_NAMESPACE_BEGIN
28 struct SynthIce40Pass
: public ScriptPass
30 SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
32 void help() YS_OVERRIDE
34 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
36 log(" synth_ice40 [options]\n");
38 log("This command runs synthesis for iCE40 FPGAs.\n");
40 log(" -device < hx | lp | u >\n");
41 log(" relevant only for '-abc9' flow, optimise timing for the specified device.\n");
42 log(" default: hx\n");
44 log(" -top <module>\n");
45 log(" use the specified module as top module\n");
47 log(" -blif <file>\n");
48 log(" write the design to the specified BLIF file. writing of an output file\n");
49 log(" is omitted if this parameter is not specified.\n");
51 log(" -edif <file>\n");
52 log(" write the design to the specified EDIF file. writing of an output file\n");
53 log(" is omitted if this parameter is not specified.\n");
55 log(" -json <file>\n");
56 log(" write the design to the specified JSON file. writing of an output file\n");
57 log(" is omitted if this parameter is not specified.\n");
59 log(" -run <from_label>:<to_label>\n");
60 log(" only run the commands between the labels (see below). an empty\n");
61 log(" from label is synonymous to 'begin', and empty to label is\n");
62 log(" synonymous to the end of the command list.\n");
65 log(" do not flatten design before synthesis\n");
68 log(" run 'abc' with '-dff -D 1' options\n");
71 log(" do not use SB_CARRY cells in output netlist\n");
74 log(" do not use SB_DFFE* cells in output netlist\n");
76 log(" -dffe_min_ce_use <min_ce_use>\n");
77 log(" do not use SB_DFFE* cells if the resulting CE line would go to less\n");
78 log(" than min_ce_use SB_DFFE* in output netlist\n");
81 log(" do not use SB_RAM40_4K* cells in output netlist\n");
84 log(" use iCE40 UltraPlus DSP cells for large arithmetic\n");
87 log(" use built-in Yosys LUT techmapping instead of abc\n");
90 log(" run two passes of 'abc' for slightly improved logic density\n");
93 log(" generate an output netlist (and BLIF file) suitable for VPR\n");
94 log(" (this feature is experimental and incomplete)\n");
97 log(" use new ABC9 flow (EXPERIMENTAL)\n");
100 log(" use FlowMap LUT techmapping instead of abc (EXPERIMENTAL)\n");
103 log("The following commands are executed by this synthesis command:\n");
108 string top_opt
, blif_file
, edif_file
, json_file
, device_opt
;
109 bool nocarry
, nodffe
, nobram
, dsp
, flatten
, retime
, noabc
, abc2
, vpr
, abc9
, flowmap
;
112 void clear_flags() YS_OVERRIDE
114 top_opt
= "-auto-top";
133 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
135 string run_from
, run_to
;
139 for (argidx
= 1; argidx
< args
.size(); argidx
++)
141 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
142 top_opt
= "-top " + args
[++argidx
];
145 if (args
[argidx
] == "-blif" && argidx
+1 < args
.size()) {
146 blif_file
= args
[++argidx
];
149 if (args
[argidx
] == "-edif" && argidx
+1 < args
.size()) {
150 edif_file
= args
[++argidx
];
153 if (args
[argidx
] == "-json" && argidx
+1 < args
.size()) {
154 json_file
= args
[++argidx
];
157 if (args
[argidx
] == "-run" && argidx
+1 < args
.size()) {
158 size_t pos
= args
[argidx
+1].find(':');
159 if (pos
== std::string::npos
)
161 run_from
= args
[++argidx
].substr(0, pos
);
162 run_to
= args
[argidx
].substr(pos
+1);
165 if (args
[argidx
] == "-flatten") {
169 if (args
[argidx
] == "-noflatten") {
173 if (args
[argidx
] == "-retime") {
177 if (args
[argidx
] == "-relut") {
178 // removed, opt_lut is always run
181 if (args
[argidx
] == "-nocarry") {
185 if (args
[argidx
] == "-nodffe") {
189 if (args
[argidx
] == "-dffe_min_ce_use" && argidx
+1 < args
.size()) {
190 min_ce_use
= atoi(args
[++argidx
].c_str());
193 if (args
[argidx
] == "-nobram") {
197 if (args
[argidx
] == "-dsp") {
201 if (args
[argidx
] == "-noabc") {
205 if (args
[argidx
] == "-abc2") {
209 if (args
[argidx
] == "-vpr") {
213 if (args
[argidx
] == "-abc9") {
217 if (args
[argidx
] == "-device" && argidx
+1 < args
.size()) {
218 device_opt
= args
[++argidx
];
221 if (args
[argidx
] == "-flowmap") {
227 extra_args(args
, argidx
, design
);
229 if (!design
->full_selection())
230 log_cmd_error("This command only operates on fully selected designs!\n");
231 if (device_opt
!= "hx" && device_opt
!= "lp" && device_opt
!="u")
232 log_cmd_error("Invalid or no device specified: '%s'\n", device_opt
.c_str());
235 log_cmd_error("-retime option not currently compatible with -abc9!\n");
238 log_cmd_error("-abc9 is incompatible with -noabc!\n");
240 log_cmd_error("-abc9 is incompatible with -flowmap!\n");
241 if (flowmap
&& noabc
)
242 log_cmd_error("-flowmap is incompatible with -noabc!\n");
244 log_header(design
, "Executing SYNTH_ICE40 pass.\n");
247 run_script(design
, run_from
, run_to
);
252 void script() YS_OVERRIDE
255 if (device_opt
== "lp")
256 define
= "-D ICE40_LP";
257 else if (device_opt
== "u")
258 define
= "-D ICE40_U";
260 define
= "-D ICE40_HX";
261 if (check_label("begin"))
263 run("read_verilog " + define
+ " -lib -specify +/ice40/cells_sim.v");
264 run(stringf("hierarchy -check %s", help_mode
? "-top <top>" : top_opt
.c_str()));
268 if (check_label("flatten", "(unless -noflatten)"))
272 run("tribuf -logic");
277 if (check_label("coarse"))
287 run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
290 if (help_mode
|| dsp
) {
291 run("memory_dff"); // ice40_dsp will merge registers, reserve memory port registers first
292 run("wreduce t:$mul");
293 run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 "
294 "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 "
295 "-D DSP_NAME=$__MUL16X16", "(if -dsp)");
296 run("select a:mul2dsp", " (if -dsp)");
297 run("setattr -unset mul2dsp", " (if -dsp)");
298 run("opt_expr -fine", " (if -dsp)");
299 run("wreduce", " (if -dsp)");
300 run("select -clear", " (if -dsp)");
301 run("ice40_dsp", " (if -dsp)");
302 run("chtype -set $mul t:$__soft_mul", "(if -dsp)");
308 run("memory -nomap");
312 if (!nobram
&& check_label("map_bram", "(skip if -nobram)"))
314 run("memory_bram -rules +/ice40/brams.txt");
315 run("techmap -map +/ice40/brams_map.v");
316 run("ice40_braminit");
319 if (check_label("map_ffram"))
321 run("opt -fast -mux_undef -undriven -fine");
322 run("memory_map -iattr -attr !ram_block -attr !rom_block -attr logic_block "
323 "-attr syn_ramstyle=auto -attr syn_ramstyle=registers "
324 "-attr syn_romstyle=auto -attr syn_romstyle=logic");
325 run("opt -undriven -fine");
328 if (check_label("map_gates"))
333 run("ice40_wrapcarry");
334 run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
337 if (retime
|| help_mode
)
338 run("abc -dff -D 1", "(only if -retime)");
342 if (check_label("map_ffs"))
346 run("dff2dffe -direct-match $_DFF_*");
347 if (min_ce_use
>= 0) {
349 run(stringf("dff2dffe -unmap-mince %d", min_ce_use
));
350 run("simplemap t:$dff");
352 run("techmap -D NO_LUT -D NO_ADDER -map +/ice40/cells_map.v");
353 run("opt_expr -mux_undef");
357 run("ice40_opt -full");
360 if (check_label("map_luts"))
362 if (abc2
|| help_mode
) {
363 run("abc", " (only if -abc2)");
364 run("ice40_opt", "(only if -abc2)");
366 run("techmap -map +/ice40/latches_map.v");
367 if (noabc
|| flowmap
|| help_mode
) {
368 run("simplemap", " (if -noabc or -flowmap)");
369 if (noabc
|| help_mode
)
370 run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
371 if (flowmap
|| help_mode
)
372 run("flowmap -maxlut 4", "(only if -flowmap)");
376 run("read_verilog " + define
+ " -icells -lib -specify +/abc9_model.v +/ice40/abc9_model.v");
378 if (device_opt
== "lp")
380 else if (device_opt
== "u")
384 run(stringf("abc9 -W %d", wire_delay
));
387 run("abc -dress -lut 4", "(skip if -noabc)");
389 run("ice40_wrapcarry -unwrap");
390 run("techmap -D NO_LUT -map +/ice40/cells_map.v");
392 run("opt_lut -dlogic SB_CARRY:I0=2:I1=1:CI=0");
395 if (check_label("map_cells"))
398 run("techmap -D NO_LUT -map +/ice40/cells_map.v");
400 run("techmap -map +/ice40/cells_map.v", "(with -D NO_LUT in vpr mode)");
405 if (check_label("check"))
408 run("hierarchy -check");
410 run("check -noinit");
413 if (check_label("blif"))
415 if (!blif_file
.empty() || help_mode
) {
416 if (vpr
|| help_mode
) {
417 run(stringf("opt_clean -purge"),
419 run(stringf("write_blif -attr -cname -conn -param %s",
420 help_mode
? "<file-name>" : blif_file
.c_str()),
424 run(stringf("write_blif -gates -attr -param %s",
425 help_mode
? "<file-name>" : blif_file
.c_str()),
430 if (check_label("edif"))
432 if (!edif_file
.empty() || help_mode
)
433 run(stringf("write_edif %s", help_mode
? "<file-name>" : edif_file
.c_str()));
436 if (check_label("json"))
438 if (!json_file
.empty() || help_mode
)
439 run(stringf("write_json %s", help_mode
? "<file-name>" : json_file
.c_str()));
444 PRIVATE_NAMESPACE_END