Merge branch 'master' of github.com:cliffordwolf/yosys
[yosys.git] / techlibs / intel / common / brams.txt
1 bram $__M9K_ALTSYNCRAM_SINGLEPORT_FULL
2 init 1
3 abits 13 @M1
4 dbits 1 @M1
5 abits 12 @M2
6 dbits 2 @M2
7 abits 11 @M3
8 dbits 4 @M3
9 abits 10 @M4
10 dbits 8 @M4
11 abits 10 @M5
12 dbits 9 @M5
13 abits 9 @M6
14 dbits 16 @M6
15 abits 9 @M7
16 dbits 18 @M7
17 abits 8 @M8
18 dbits 32 @M8
19 abits 8 @M9
20 dbits 36 @M9
21 groups 2
22 ports 1 1
23 wrmode 0 1
24 enable 1 1
25 transp 0 0
26 clocks 2 3
27 clkpol 2 3
28 endbram
29
30 match $__M9K_ALTSYNCRAM_SINGLEPORT_FULL
31 min efficiency 2
32 make_transp
33 endmatch