1 module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
3 parameter CFG_ABITS = 8;
4 parameter CFG_DBITS = 36;
13 output [CFG_DBITS-1:0] A1DATA;
14 input [CFG_ABITS-1:0] A1ADDR;
17 output [CFG_DBITS-1:0] B1DATA;
18 input [CFG_ABITS-1:0] B1ADDR;
21 wire [CFG_DBITS-1:0] B1DATA_t;
23 localparam MODE = CFG_DBITS == 1 ? 1:
34 localparam NUMWORDS = CFG_DBITS == 1 ? "8192":
35 CFG_DBITS == 2 ? "4096":
36 CFG_DBITS == 4 ? "2048":
37 CFG_DBITS == 8 ? "1024":
38 CFG_DBITS == 9 ? "1024":
39 CFG_DBITS == 16 ? "512":
40 CFG_DBITS == 18 ? "512":
41 CFG_DBITS == 32 ? "256":
42 CFG_DBITS == 36 ? "256":
44 /* Killing some stupid warnings and assignations*/
47 assign B1DATA_t = ({34{1'b0},B1DATA[0]});
51 altsyncram #(.clock_enable_input_b ("ALTERNATE" ),
52 .clock_enable_input_a ("ALTERNATE" ),
53 .clock_enable_output_b ("NORMAL" ),
54 .clock_enable_output_a ("NORMAL" ),
55 .wrcontrol_aclr_a ("NONE" ),
56 .indata_aclr_a ("NONE" ),
57 .address_aclr_a ("NONE" ),
58 .outdata_aclr_a ("NONE" ),
59 .outdata_reg_a ("UNREGISTERED"),
60 .operation_mode ("SINGLE_PORT" ),
61 .intended_device_family ("CYCLONE IVE" ),
62 .outdata_reg_a ("UNREGISTERED"),
63 .lpm_type ("altsyncram" ),
64 .init_type ("unused" ),
65 .ram_block_type ("AUTO" ),
66 .numwords_b ( NUMWORDS ),
67 .numwords_a ( NUMWORDS ),
68 .widthad_b ( CFG_ABITS ),
69 .width_b ( CFG_DBITS ),
70 .widthad_a ( CFG_ABITS ),
71 .width_a ( CFG_DBITS )
84 .clock1(1'b1), // Unused in single port mode
91 .addressstall_a(1'b0),
92 .addressstall_b(1'b0));