techlibs/intel/common/brams_map.v

   1 module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
   2
   3    parameter CFG_ABITS = 8;
   4    parameter CFG_DBITS = 36;
   5    parameter ABITS = "1";
   6    parameter DBITS = "1";
   7    parameter CLKPOL2 = 1;
   8    parameter CLKPOL3 = 1;
   9
  10    input CLK2;
  11    input CLK3;
  12    //Read data
  13    output [CFG_DBITS-1:0] A1DATA;
  14    input [CFG_ABITS-1:0]  A1ADDR;
  15    input                  A1EN;
  16    //Write data
  17    output [CFG_DBITS-1:0] B1DATA;
  18    input [CFG_ABITS-1:0]  B1ADDR;
  19    input                  B1EN;
  20
  21    wire [CFG_DBITS-1:0]   B1DATA_t;
  22
  23    localparam MODE = CFG_DBITS == 1  ? 1:
  24                      CFG_DBITS == 2  ? 2:
  25                      CFG_DBITS == 4  ? 3:
  26                      CFG_DBITS == 8  ? 4:
  27                      CFG_DBITS == 9  ? 5:
  28                      CFG_DBITS == 16 ? 6:
  29                      CFG_DBITS == 18 ? 7:
  30                      CFG_DBITS == 32 ? 8:
  31                      CFG_DBITS == 36 ? 9:
  32                      'bx;
  33
  34    localparam NUMWORDS = CFG_DBITS == 1  ? "8192":
  35                          CFG_DBITS == 2  ? "4096":
  36                          CFG_DBITS == 4  ? "2048":
  37                          CFG_DBITS == 8  ? "1024":
  38                          CFG_DBITS == 9  ? "1024":
  39                          CFG_DBITS == 16 ?  "512":
  40                          CFG_DBITS == 18 ?  "512":
  41                          CFG_DBITS == 32 ?  "256":
  42                          CFG_DBITS == 36 ?  "256":
  43                          'bx;
  44    /* Killing some stupid warnings and assignations*/
  45   /* generate
  46       if( MODE == 1 ) begin
  47          assign B1DATA_t = ({34{1'b0},B1DATA[0]});
  48       end
  49    endgenerate*/
  50
  51    altsyncram  #(.clock_enable_input_b   ("ALTERNATE"   ),
  52                  .clock_enable_input_a   ("ALTERNATE"   ),
  53                  .clock_enable_output_b  ("NORMAL"      ),
  54                  .clock_enable_output_a  ("NORMAL"      ),
  55                  .wrcontrol_aclr_a       ("NONE"        ),
  56                  .indata_aclr_a          ("NONE"        ),
  57                  .address_aclr_a         ("NONE"        ),
  58                  .outdata_aclr_a         ("NONE"        ),
  59                  .outdata_reg_a          ("UNREGISTERED"),
  60                  .operation_mode         ("SINGLE_PORT" ),
  61                  .intended_device_family ("CYCLONE IVE" ),
  62                  .outdata_reg_a          ("UNREGISTERED"),
  63                  .lpm_type               ("altsyncram"  ),
  64                  .init_type              ("unused"      ),
  65                  .ram_block_type         ("AUTO"        ),
  66                  .numwords_b             ( NUMWORDS     ),
  67                  .numwords_a             ( NUMWORDS     ),
  68                  .widthad_b              ( CFG_ABITS    ),
  69                  .width_b                ( CFG_DBITS    ),
  70                  .widthad_a              ( CFG_ABITS    ),
  71                  .width_a                ( CFG_DBITS    )
  72                  ) _TECHMAP_REPLACE_ (
  73                                       .data_a(B1DATA),
  74                                       .address_a(B1ADDR),
  75                                       .wren_a(B1EN),
  76                                       .rden_a(A1EN),
  77                                       .q_a(A1DATA),
  78                                       .data_b(1'b0),
  79                                       .address_b(0),
  80                                       .wren_b(1'b0),
  81                                       .rden_b(1'b0),
  82                                       .q_b(1'b0),
  83                                       .clock0(CLK2),
  84                                       .clock1(1'b1), // Unused in single port mode
  85                                       .clocken0(1'b1),
  86                                       .clocken1(1'b1),
  87                                       .clocken2(1'b1),
  88                                       .clocken3(1'b1),
  89                                       .aclr0(1'b0),
  90                                       .aclr1(1'b0),
  91                                       .addressstall_a(1'b0),
  92                                       .addressstall_b(1'b0));
  93
  94 endmodule
  95