techlibs/intel/common/brams_map.v

   1 module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
   2
   3    parameter CFG_ABITS = 8;
   4    parameter CFG_DBITS = 36;
   5    parameter ABITS = "1";
   6    parameter DBITS = "1";
   7    parameter CLKPOL2 = 1;
   8    parameter CLKPOL3 = 1;
   9
  10    input CLK2;
  11    input CLK3;
  12    //Read data
  13    output [CFG_DBITS-1:0] A1DATA;
  14    input [CFG_ABITS-1:0]  A1ADDR;
  15    input                  A1EN;
  16    //Write data
  17    output [CFG_DBITS-1:0] B1DATA;
  18    input [CFG_ABITS-1:0]  B1ADDR;
  19    input                  B1EN;
  20
  21    wire [CFG_DBITS-1:0]   B1DATA_t;
  22
  23    localparam MODE = CFG_DBITS == 1  ? 1:
  24                      CFG_DBITS == 2  ? 2:
  25                      CFG_DBITS == 4  ? 3:
  26                      CFG_DBITS == 8  ? 4:
  27                      CFG_DBITS == 9  ? 5:
  28                      CFG_DBITS == 16 ? 6:
  29                      CFG_DBITS == 18 ? 7:
  30                      CFG_DBITS == 32 ? 8:
  31                      CFG_DBITS == 36 ? 9:
  32                      'bx;
  33
  34    localparam NUMWORDS = CFG_DBITS == 1  ? 8192:
  35                          CFG_DBITS == 2  ? 4096:
  36                          CFG_DBITS == 4  ? 2048:
  37                          CFG_DBITS == 8  ? 1024:
  38                          CFG_DBITS == 9  ? 1024:
  39                          CFG_DBITS == 16 ?  512:
  40                          CFG_DBITS == 18 ?  512:
  41                          CFG_DBITS == 32 ?  256:
  42                          CFG_DBITS == 36 ?  256:
  43                          'bx;
  44
  45    altsyncram  #(.clock_enable_input_b           ("ALTERNATE"   ),
  46                  .clock_enable_input_a           ("ALTERNATE"   ),
  47                  .clock_enable_output_b          ("NORMAL"      ),
  48                  .clock_enable_output_a          ("NORMAL"      ),
  49                  .wrcontrol_aclr_a               ("NONE"        ),
  50                  .indata_aclr_a                  ("NONE"        ),
  51                  .address_aclr_a                 ("NONE"        ),
  52                  .outdata_aclr_a                 ("NONE"        ),
  53                  .outdata_reg_a                  ("UNREGISTERED"),
  54                  .operation_mode                 ("SINGLE_PORT" ),
  55                  .intended_device_family         ("CYCLONE IVE" ),
  56                  .outdata_reg_a                  ("UNREGISTERED"),
  57                  .lpm_type                       ("altsyncram"  ),
  58                  .init_type                      ("unused"      ),
  59                  .ram_block_type                 ("AUTO"        ),
  60                  .lpm_hint                       ("ENABLE_RUNTIME_MOD=NO"), // Forced value
  61                  .power_up_uninitialized         ("FALSE"),
  62                  .read_during_write_mode_port_a  ("NEW_DATA_NO_NBE_READ"), // Forced value
  63                  .width_byteena_a                (1), // Forced value
  64                  .numwords_b                     ( NUMWORDS     ),
  65                  .numwords_a                     ( NUMWORDS     ),
  66                  .widthad_b                      ( CFG_ABITS    ),
  67                  .width_b                        ( CFG_DBITS    ),
  68                  .widthad_a                      ( CFG_ABITS    ),
  69                  .width_a                        ( CFG_DBITS    )
  70                  ) _TECHMAP_REPLACE_ (
  71                                       .data_a(B1DATA),
  72                                       .address_a(B1ADDR),
  73                                       .wren_a(B1EN),
  74                                       .rden_a(A1EN),
  75                                       .q_a(A1DATA),
  76                                       .data_b(1'b0),
  77                                       .address_b(0),
  78                                       .wren_b(1'b0),
  79                                       .rden_b(1'b0),
  80                                       .q_b(1'b0),
  81                                       .clock0(CLK2),
  82                                       .clock1(1'b1), // Unused in single port mode
  83                                       .clocken0(1'b1),
  84                                       .clocken1(1'b1),
  85                                       .clocken2(1'b1),
  86                                       .clocken3(1'b1),
  87                                       .aclr0(1'b0),
  88                                       .aclr1(1'b0),
  89                                       .addressstall_a(1'b0),
  90                                       .addressstall_b(1'b0));
  91
  92 endmodule
  93