1 module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
3 parameter CFG_ABITS = 8;
4 parameter CFG_DBITS = 36;
13 output [CFG_DBITS-1:0] A1DATA;
14 input [CFG_ABITS-1:0] A1ADDR;
17 output [CFG_DBITS-1:0] B1DATA;
18 input [CFG_ABITS-1:0] B1ADDR;
21 wire [CFG_DBITS-1:0] B1DATA_t;
23 localparam MODE = CFG_DBITS == 1 ? 1:
34 localparam NUMWORDS = CFG_DBITS == 1 ? 8192:
35 CFG_DBITS == 2 ? 4096:
36 CFG_DBITS == 4 ? 2048:
37 CFG_DBITS == 8 ? 1024:
38 CFG_DBITS == 9 ? 1024:
39 CFG_DBITS == 16 ? 512:
40 CFG_DBITS == 18 ? 512:
41 CFG_DBITS == 32 ? 256:
42 CFG_DBITS == 36 ? 256:
45 altsyncram #(.clock_enable_input_b ("ALTERNATE" ),
46 .clock_enable_input_a ("ALTERNATE" ),
47 .clock_enable_output_b ("NORMAL" ),
48 .clock_enable_output_a ("NORMAL" ),
49 .wrcontrol_aclr_a ("NONE" ),
50 .indata_aclr_a ("NONE" ),
51 .address_aclr_a ("NONE" ),
52 .outdata_aclr_a ("NONE" ),
53 .outdata_reg_a ("UNREGISTERED"),
54 .operation_mode ("SINGLE_PORT" ),
55 .intended_device_family ("CYCLONE IVE" ),
56 .outdata_reg_a ("UNREGISTERED"),
57 .lpm_type ("altsyncram" ),
58 .init_type ("unused" ),
59 .ram_block_type ("AUTO" ),
60 .lpm_hint ("ENABLE_RUNTIME_MOD=NO"), // Forced value
61 .power_up_uninitialized ("FALSE"),
62 .read_during_write_mode_port_a ("NEW_DATA_NO_NBE_READ"), // Forced value
63 .width_byteena_a (1), // Forced value
64 .numwords_b ( NUMWORDS ),
65 .numwords_a ( NUMWORDS ),
66 .widthad_b ( CFG_DBITS ),
67 .width_b ( CFG_ABITS ),
68 .widthad_a ( CFG_DBITS ),
69 .width_a ( CFG_ABITS )
82 .clock1(1'b1), // Unused in single port mode
89 .addressstall_a(1'b0),
90 .addressstall_b(1'b0));