2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/celltypes.h"
21 #include "kernel/log.h"
22 #include "kernel/register.h"
23 #include "kernel/rtlil.h"
26 PRIVATE_NAMESPACE_BEGIN
28 struct SynthIntelPass
: public ScriptPass
{
29 SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") {}
31 void help() YS_OVERRIDE
33 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
35 log(" synth_intel [options]\n");
37 log("This command runs synthesis for Intel FPGAs.\n");
39 log(" -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n");
40 log(" generate the synthesis netlist for the specified family.\n");
41 log(" MAX10 is the default target if not family argument specified.\n");
42 log(" For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n");
43 log(" Cyclone V and Arria 10 GX devices are experimental, use it with a10gx argument.\n");
45 log(" -top <module>\n");
46 log(" use the specified module as top module (default='top')\n");
48 log(" -vqm <file>\n");
49 log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n");
50 log(" output file is omitted if this parameter is not specified.\n");
52 log(" -vpr <file>\n");
53 log(" write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n");
54 log(" compatible with the Quartus flow. Writing of an\n");
55 log(" output file is omitted if this parameter is not specified.\n");
57 log(" -run <from_label>:<to_label>\n");
58 log(" only run the commands between the labels (see below). an empty\n");
59 log(" from label is synonymous to 'begin', and empty to label is\n");
60 log(" synonymous to the end of the command list.\n");
63 log(" do not use altsyncram cells in output netlist\n");
66 log(" do not use altsyncram cells in output netlist\n");
69 log(" do not flatten design before synthesis\n");
72 log(" run 'abc' with -dff option\n");
74 log("The following commands are executed by this synthesis command:\n");
79 string top_opt
, family_opt
, vout_file
, blif_file
;
80 bool retime
, flatten
, nobram
, noiopads
;
82 void clear_flags() YS_OVERRIDE
84 top_opt
= "-auto-top";
94 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
96 string run_from
, run_to
;
100 for (argidx
= 1; argidx
< args
.size(); argidx
++) {
101 if (args
[argidx
] == "-family" && argidx
+ 1 < args
.size()) {
102 family_opt
= args
[++argidx
];
105 if (args
[argidx
] == "-top" && argidx
+ 1 < args
.size()) {
106 top_opt
= "-top " + args
[++argidx
];
109 if (args
[argidx
] == "-vqm" && argidx
+ 1 < args
.size()) {
110 vout_file
= args
[++argidx
];
113 if (args
[argidx
] == "-vpr" && argidx
+ 1 < args
.size()) {
114 blif_file
= args
[++argidx
];
117 if (args
[argidx
] == "-run" && argidx
+ 1 < args
.size()) {
118 size_t pos
= args
[argidx
+ 1].find(':');
119 if (pos
== std::string::npos
)
121 run_from
= args
[++argidx
].substr(0, pos
);
122 run_to
= args
[argidx
].substr(pos
+ 1);
125 if (args
[argidx
] == "-noiopads") {
129 if (args
[argidx
] == "-nobram") {
133 if (args
[argidx
] == "-noflatten") {
137 if (args
[argidx
] == "-retime") {
143 extra_args(args
, argidx
, design
);
145 if (!design
->full_selection())
146 log_cmd_error("This command only operates on fully selected designs!\n");
147 if (family_opt
!= "max10" && family_opt
!= "a10gx" && family_opt
!= "cyclonev" && family_opt
!= "cycloneiv" &&
148 family_opt
!= "cycloneive" && family_opt
!= "cyclone10")
149 log_cmd_error("Invalid or not family specified: '%s'\n", family_opt
.c_str());
151 log_header(design
, "Executing SYNTH_INTEL pass.\n");
154 run_script(design
, run_from
, run_to
);
159 void script() YS_OVERRIDE
161 if (check_label("begin")) {
162 if (check_label("family") && family_opt
== "max10")
163 run("read_verilog -sv -lib +/intel/max10/cells_sim.v");
164 else if (check_label("family") && family_opt
== "a10gx")
165 run("read_verilog -sv -lib +/intel/a10gx/cells_sim.v");
166 else if (check_label("family") && family_opt
== "cyclonev")
167 run("read_verilog -sv -lib +/intel/cyclonev/cells_sim.v");
168 else if (check_label("family") && family_opt
== "cyclone10")
169 run("read_verilog -sv -lib +/intel/cyclone10/cells_sim.v");
170 else if (check_label("family") && family_opt
== "cycloneiv")
171 run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v");
173 run("read_verilog -sv -lib +/intel/cycloneive/cells_sim.v");
174 // Misc and common cells
175 run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
176 run("read_verilog -sv -lib +/intel/common/altpll_bb.v");
177 run(stringf("hierarchy -check %s", help_mode
? "-top <top>" : top_opt
.c_str()));
180 if (flatten
&& check_label("flatten", "(unless -noflatten)")) {
183 run("tribuf -logic");
187 if (check_label("coarse")) {
188 run("synth -run coarse");
191 if (!nobram
&& check_label("bram", "(skip if -nobram)")) {
192 run("memory_bram -rules +/intel/common/brams.txt");
193 run("techmap -map +/intel/common/brams_map.v");
196 if (check_label("fine")) {
197 run("opt -fast -mux_undef -undriven -fine -full");
199 run("opt -undriven -fine");
201 run("dff2dffe -direct-match $_DFF_*");
203 run("techmap -map +/techmap.v");
206 run("setundef -undriven -zero");
207 if (retime
|| help_mode
)
208 run("abc -markgroups -dff", "(only if -retime)");
211 if (check_label("map_luts")) {
212 if (family_opt
== "a10gx" || family_opt
== "cyclonev")
213 run("abc -luts 2:2,3,6:5" + string(retime
? " -dff" : ""));
215 run("abc -lut 4" + string(retime
? " -dff" : ""));
219 if (check_label("map_cells")) {
221 run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)");
222 if (family_opt
== "max10")
223 run("techmap -map +/intel/max10/cells_map.v");
224 else if (family_opt
== "a10gx")
225 run("techmap -map +/intel/a10gx/cells_map.v");
226 else if (family_opt
== "cyclonev")
227 run("techmap -map +/intel/cyclonev/cells_map.v");
228 else if (family_opt
== "cyclone10")
229 run("techmap -map +/intel/cyclone10/cells_map.v");
230 else if (family_opt
== "cycloneiv")
231 run("techmap -map +/intel/cycloneiv/cells_map.v");
233 run("techmap -map +/intel/cycloneive/cells_map.v");
234 run("dffinit -highlow -ff dffeas q power_up");
238 if (check_label("check")) {
239 run("hierarchy -check");
241 run("check -noinit");
244 if (check_label("vqm")) {
245 if (!vout_file
.empty() || help_mode
)
246 run(stringf("write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ %s",
247 help_mode
? "<file-name>" : vout_file
.c_str()));
250 if (check_label("vpr")) {
251 if (!blif_file
.empty() || help_mode
) {
252 run(stringf("opt_clean -purge"));
253 run(stringf("write_blif %s", help_mode
? "<file-name>" : blif_file
.c_str()));
259 PRIVATE_NAMESPACE_END