techlibs/intel/synth_intel.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/celltypes.h"
  21 #include "kernel/log.h"
  22 #include "kernel/register.h"
  23 #include "kernel/rtlil.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 struct SynthIntelPass : public ScriptPass {
  29         SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") { experimental(); }
  30
  31         void help() YS_OVERRIDE
  32         {
  33                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  34                 log("\n");
  35                 log("    synth_intel [options]\n");
  36                 log("\n");
  37                 log("This command runs synthesis for Intel FPGAs.\n");
  38                 log("\n");
  39                 log("    -family <max10 | arria10gx | cyclone10lp | cyclonev | cycloneiv | cycloneive>\n");
  40                 log("        generate the synthesis netlist for the specified family.\n");
  41                 log("        MAX10 is the default target if no family argument specified.\n");
  42                 log("        For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use cycloneive.\n");
  43                 log("        Cyclone V and Arria 10 GX devices are experimental.\n");
  44                 log("\n");
  45                 log("    -top <module>\n");
  46                 log("        use the specified module as top module (default='top')\n");
  47                 log("\n");
  48                 log("    -vqm <file>\n");
  49                 log("        write the design to the specified Verilog Quartus Mapping File. Writing of an\n");
  50                 log("        output file is omitted if this parameter is not specified.\n");
  51                 log("        Note that this backend has not been tested and is likely incompatible\n");
  52                 log("        with recent versions of Quartus.\n");
  53                 log("\n");
  54                 log("    -vpr <file>\n");
  55                 log("        write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n");
  56                 log("        compatible with the Quartus flow. Writing of an\n");
  57                 log("        output file is omitted if this parameter is not specified.\n");
  58                 log("\n");
  59                 log("    -run <from_label>:<to_label>\n");
  60                 log("        only run the commands between the labels (see below). an empty\n");
  61                 log("        from label is synonymous to 'begin', and empty to label is\n");
  62                 log("        synonymous to the end of the command list.\n");
  63                 log("\n");
  64                 log("    -iopads\n");
  65                 log("        use IO pad cells in output netlist\n");
  66                 log("\n");
  67                 log("    -nobram\n");
  68                 log("        do not use block RAM cells in output netlist\n");
  69                 log("\n");
  70                 log("    -noflatten\n");
  71                 log("        do not flatten design before synthesis\n");
  72                 log("\n");
  73                 log("    -retime\n");
  74                 log("        run 'abc' with '-dff -D 1' options\n");
  75                 log("\n");
  76                 log("The following commands are executed by this synthesis command:\n");
  77                 help_script();
  78                 log("\n");
  79         }
  80
  81         string top_opt, family_opt, vout_file, blif_file;
  82         bool retime, flatten, nobram, iopads;
  83
  84         void clear_flags() YS_OVERRIDE
  85         {
  86                 top_opt = "-auto-top";
  87                 family_opt = "max10";
  88                 vout_file = "";
  89                 blif_file = "";
  90                 retime = false;
  91                 flatten = true;
  92                 nobram = false;
  93                 iopads = false;
  94         }
  95
  96         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
  97         {
  98                 string run_from, run_to;
  99                 clear_flags();
 100
 101                 size_t argidx;
 102                 for (argidx = 1; argidx < args.size(); argidx++) {
 103                         if (args[argidx] == "-family" && argidx + 1 < args.size()) {
 104                                 family_opt = args[++argidx];
 105                                 continue;
 106                         }
 107                         if (args[argidx] == "-top" && argidx + 1 < args.size()) {
 108                                 top_opt = "-top " + args[++argidx];
 109                                 continue;
 110                         }
 111                         if (args[argidx] == "-vqm" && argidx + 1 < args.size()) {
 112                                 vout_file = args[++argidx];
 113                                 log_warning("The Quartus backend has not been tested recently and is likely incompatible with modern versions of Quartus.\n");
 114                                 continue;
 115                         }
 116                         if (args[argidx] == "-vpr" && argidx + 1 < args.size()) {
 117                                 blif_file = args[++argidx];
 118                                 continue;
 119                         }
 120                         if (args[argidx] == "-run" && argidx + 1 < args.size()) {
 121                                 size_t pos = args[argidx + 1].find(':');
 122                                 if (pos == std::string::npos)
 123                                         break;
 124                                 run_from = args[++argidx].substr(0, pos);
 125                                 run_to = args[argidx].substr(pos + 1);
 126                                 continue;
 127                         }
 128                         if (args[argidx] == "-iopads") {
 129                                 iopads = true;
 130                                 continue;
 131                         }
 132                         if (args[argidx] == "-nobram") {
 133                                 nobram = true;
 134                                 continue;
 135                         }
 136                         if (args[argidx] == "-noflatten") {
 137                                 flatten = false;
 138                                 continue;
 139                         }
 140                         if (args[argidx] == "-retime") {
 141                                 retime = true;
 142                                 continue;
 143                         }
 144                         break;
 145                 }
 146                 extra_args(args, argidx, design);
 147
 148                 if (!design->full_selection())
 149                         log_cmd_error("This command only operates on fully selected designs!\n");
 150                 if (family_opt != "max10" &&
 151                     family_opt != "arria10gx" &&
 152                     family_opt != "cyclonev" &&
 153                     family_opt != "cycloneiv" &&
 154                     family_opt != "cycloneive" &&
 155                     family_opt != "cyclone10lp")
 156                         log_cmd_error("Invalid or no family specified: '%s'\n", family_opt.c_str());
 157
 158                 log_header(design, "Executing SYNTH_INTEL pass.\n");
 159                 log_push();
 160
 161                 run_script(design, run_from, run_to);
 162
 163                 log_pop();
 164         }
 165
 166         void script() YS_OVERRIDE
 167         {
 168                 if (check_label("begin")) {
 169                         if (check_label("family"))
 170                                 run(stringf("read_verilog -sv -lib +/intel/%s/cells_sim.v", family_opt.c_str()));
 171
 172                         // Misc and common cells
 173                         run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
 174                         run("read_verilog -sv -lib +/intel/common/altpll_bb.v");
 175                         run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 176                 }
 177
 178                 if (flatten && check_label("flatten", "(unless -noflatten)")) {
 179                         run("proc");
 180                         run("flatten");
 181                         run("tribuf -logic");
 182                         run("deminout");
 183                 }
 184
 185                 if (check_label("coarse")) {
 186                         run("synth -run coarse");
 187                 }
 188
 189                 if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
 190                                 if (family_opt == "cycloneiv" ||
 191                                     family_opt == "cycloneive" ||
 192                                     family_opt == "max10" ||
 193                                     help_mode) {
 194                                 run("memory_bram -rules +/intel/common/brams_m9k.txt", "(if applicable for family)");
 195                                 run("techmap -map +/intel/common/brams_map_m9k.v", "(if applicable for family)");
 196                         } else {
 197                                 log_warning("BRAM mapping is not currently supported for %s.\n", family_opt.c_str());
 198                         }
 199                 }
 200
 201                 if (check_label("map_ffram")) {
 202                         run("opt -fast -mux_undef -undriven -fine -full");
 203                         run("memory_map");
 204                         run("opt -undriven -fine");
 205                         run("dff2dffe -direct-match $_DFF_*");
 206                         run("opt -fine");
 207                         run("techmap -map +/techmap.v");
 208                         run("opt -full");
 209                         run("clean -purge");
 210                         run("setundef -undriven -zero");
 211                         if (retime || help_mode)
 212                                 run("abc -markgroups -dff -D 1", "(only if -retime)");
 213                 }
 214
 215                 if (check_label("map_luts")) {
 216                         if (family_opt == "arria10gx" || family_opt == "cyclonev")
 217                                 run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
 218                         else
 219                                 run("abc -lut 4" + string(retime ? " -dff" : ""));
 220                         run("clean");
 221                 }
 222
 223                 if (check_label("map_cells")) {
 224                         if (iopads || help_mode)
 225                                 run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(if -iopads)");
 226                         run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str()));
 227                         run("dffinit -highlow -ff dffeas q power_up");
 228                         run("clean -purge");
 229                 }
 230
 231                 if (check_label("check")) {
 232                         run("hierarchy -check");
 233                         run("stat");
 234                         run("check -noinit");
 235                 }
 236
 237                 if (check_label("vqm")) {
 238                         if (!vout_file.empty() || help_mode)
 239                                 run(stringf("write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ %s",
 240                                             help_mode ? "<file-name>" : vout_file.c_str()));
 241                 }
 242
 243                 if (check_label("vpr")) {
 244                         if (!blif_file.empty() || help_mode) {
 245                                 run(stringf("opt_clean -purge"));
 246                                 run(stringf("write_blif %s", help_mode ? "<file-name>" : blif_file.c_str()));
 247                         }
 248                 }
 249         }
 250 } SynthIntelPass;
 251
 252 PRIVATE_NAMESPACE_END