techlibs/nexus/arith_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
   5  *  Copyright (C) 2018  gatecat <gatecat@ds0.me>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 (* techmap_celltype = "$alu" *)
  22 module _80_nexus_alu (A, B, CI, BI, X, Y, CO);
  23         parameter A_SIGNED = 0;
  24         parameter B_SIGNED = 0;
  25         parameter A_WIDTH = 1;
  26         parameter B_WIDTH = 1;
  27         parameter Y_WIDTH = 1;
  28
  29         (* force_downto *)
  30         input [A_WIDTH-1:0] A;
  31         (* force_downto *)
  32         input [B_WIDTH-1:0] B;
  33         (* force_downto *)
  34         output [Y_WIDTH-1:0] X, Y;
  35
  36         input CI, BI;
  37         (* force_downto *)
  38         output [Y_WIDTH-1:0] CO;
  39
  40         wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
  41
  42         (* force_downto *)
  43         wire [Y_WIDTH-1:0] A_buf, B_buf;
  44         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
  45         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
  46
  47         function integer round_up2;
  48                 input integer N;
  49                 begin
  50                         round_up2 = ((N + 1) / 2) * 2;
  51                 end
  52         endfunction
  53
  54         localparam Y_WIDTH2 = round_up2(Y_WIDTH);
  55
  56         (* force_downto *)
  57         wire [Y_WIDTH2-1:0] AA = A_buf;
  58         (* force_downto *)
  59         wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;
  60         (* force_downto *)
  61         wire [Y_WIDTH2-1:0] BX = B_buf;
  62         (* force_downto *)
  63         wire [Y_WIDTH2+1:0] FCO, Y1;
  64
  65         genvar i;
  66
  67         // Carry feed-in
  68         CCU2 #(
  69                 .INIT0("0xFFFF"),
  70                 .INIT1("0x00AA"),
  71                 .INJECT("NO")
  72         ) ccu2c_i (
  73                 .A0(1'b1), .B0(1'b1), .C0(1'b1), .D0(1'b1),
  74                 .A1(CI), .B1(1'b1), .C1(1'b1), .D1(1'b1),
  75                 .COUT(FCO[0])
  76         );
  77
  78         generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice
  79                 CCU2 #(
  80                         .INIT0("0x96AA"),
  81                         .INIT1("0x96AA"),
  82                         .INJECT("NO")
  83                 ) ccu2c_i (
  84                         .CIN(FCO[i]),
  85                         .A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b1),
  86                         .A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b1),
  87                         .S0(Y[i]), .S1(Y1[i]),
  88                         .COUT(FCO[i+2])
  89                 );
  90
  91                 assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));
  92                 if (i+1 < Y_WIDTH) begin
  93                         assign CO[i + 1] = (AA[i + 1] && BB[i + 1]) || ((Y[i + 1] ^ AA[i + 1] ^ BB[i + 1]) && (AA[i + 1] || BB[i + 1]));
  94                         assign Y[i+1] = Y1[i];
  95                 end
  96         end endgenerate
  97
  98         assign X = AA ^ BB;
  99 endmodule