techlibs/nexus/lrams_map.v

   1 module \$__NX_PDPSC512K (CLK2, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
   2         parameter CFG_ABITS = 14;
   3         parameter CFG_DBITS = 32;
   4         parameter CFG_ENABLE_A = 4;
   5
   6         parameter CLKPOL2 = 1;
   7         parameter [524287:0] INIT = 524287'b0;
   8
   9         input CLK2;
  10
  11         input [CFG_ABITS-1:0] A1ADDR;
  12         input [CFG_DBITS-1:0] A1DATA;
  13         input [CFG_ENABLE_A-1:0] A1EN;
  14
  15         input [CFG_ABITS-1:0] B1ADDR;
  16         output [CFG_DBITS-1:0] B1DATA;
  17         input B1EN;
  18
  19         wire clk;
  20         wire [31:0] rd;
  21         assign B1DATA = rd[CFG_DBITS-1:0];
  22
  23         generate
  24                 if (CLKPOL2)
  25                         assign clk = CLK2;
  26                 else
  27                         INV clk_inv_i (.A(CLK2), .Z(clk));
  28         endgenerate
  29
  30         wire we = |A1EN;
  31
  32         localparam INIT_CHUNK_SIZE = 4096;
  33
  34         function [5119:0] permute_init;
  35                 input [INIT_CHUNK_SIZE-1:0] chunk;
  36                 integer i;
  37                 begin
  38                         for (i = 0; i < 128; i = i + 1'b1)
  39                                 permute_init[i * 40 +: 40] = {8'b0, chunk[i * 32 +: 32]};
  40                 end
  41         endfunction
  42
  43         generate
  44                 PDPSC512K #(
  45                         .OUTREG("NO_REG"),
  46                         .ECC_BYTE_SEL("BYTE_EN"),
  47 `include "lrams_init.vh"
  48                         .GSR("DISABLED")
  49                 ) _TECHMAP_REPLACE_ (
  50                         .CLK(clk), .RSTR(1'b0),
  51                         .DI(A1DATA), .ADW(A1ADDR), .CEW(we), .WE(we), .CSW(1'b1),
  52                         .ADR(B1ADDR), .DO(rd), .CER(B1EN), .CSR(1'b1),
  53                 );
  54         endgenerate
  55
  56 endmodule