techlibs/quicklogic/lut_sim.v

   1 (* abc9_lut=1, lib_whitebox *)
   2 module LUT1 (
   3   output O,
   4   input I0
   5 );
   6   parameter [1:0] INIT = 0;
   7   parameter EQN = "(I0)";
   8
   9   // These timings are for PolarPro 3E; other families will need updating.
  10   specify
  11     (I0 => O) = 698; // FS -> FZ
  12   endspecify
  13
  14   assign O = I0 ? INIT[1] : INIT[0];
  15 endmodule
  16
  17 //               TZ        TSL TAB
  18 (* abc9_lut=2, lib_whitebox *)
  19 module LUT2 (
  20   output O,
  21   input I0, I1
  22 );
  23   parameter [3:0] INIT = 4'h0;
  24   parameter EQN = "(I0)";
  25
  26   // These timings are for PolarPro 3E; other families will need updating.
  27   specify
  28     (I0 => O) = 1251; // TAB -> TZ
  29     (I1 => O) = 1406; // TSL -> TZ
  30   endspecify
  31
  32   wire [1:0] s1 = I1 ? INIT[3:2] : INIT[1:0];
  33   assign O = I0 ? s1[1] : s1[0];
  34 endmodule
  35
  36 (* abc9_lut=2, lib_whitebox *)
  37 module LUT3 (
  38   output O,
  39   input I0, I1, I2
  40 );
  41   parameter [7:0] INIT = 8'h0;
  42   parameter EQN = "(I0)";
  43
  44   // These timings are for PolarPro 3E; other families will need updating.
  45   specify
  46     (I0 => O) = 1251; // TAB -> TZ
  47     (I1 => O) = 1406; // TSL -> TZ
  48     (I2 => O) = 1699; // ('TA1', 'TA2', 'TB1', 'TB2') -> TZ
  49   endspecify
  50
  51   wire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0];
  52   wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
  53   assign O = I0 ? s1[1] : s1[0];
  54 endmodule
  55
  56 (* abc9_lut=4, lib_whitebox *)
  57 module LUT4 (
  58   output O,
  59   input I0, I1, I2, I3
  60 );
  61   parameter [15:0] INIT = 16'h0;
  62   parameter EQN = "(I0)";
  63
  64   // These timings are for PolarPro 3E; other families will need updating.
  65   specify
  66     (I0 => O) = 995;  // TBS -> CZ
  67     (I1 => O) = 1437; // ('TAB', 'BAB') -> CZ
  68     (I2 => O) = 1593; // ('TSL', 'BSL') -> CZ
  69     (I3 => O) = 1887; // ('TA1', 'TA2', 'TB1', 'TB2', 'BA1', 'BA2', 'BB1', 'BB2') -> CZ
  70   endspecify
  71
  72   wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0];
  73   wire [3:0] s2 = I2 ? s3[7:4] : s3[3:0];
  74   wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
  75   assign O = I0 ? s1[1] : s1[0];
  76 endmodule