techlibs/quicklogic/synth_quicklogic.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2021 QuickLogic Corp.
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19 #include "kernel/celltypes.h"
  20 #include "kernel/log.h"
  21 #include "kernel/register.h"
  22 #include "kernel/rtlil.h"
  23
  24 USING_YOSYS_NAMESPACE
  25 PRIVATE_NAMESPACE_BEGIN
  26
  27 struct SynthQuickLogicPass : public ScriptPass {
  28
  29         SynthQuickLogicPass() : ScriptPass("synth_quicklogic", "Synthesis for QuickLogic FPGAs") {}
  30
  31         void help() override
  32         {
  33                 log("\n");
  34                 log("   synth_quicklogic [options]\n");
  35                 log("This command runs synthesis for QuickLogic FPGAs\n");
  36                 log("\n");
  37                 log("    -top <module>\n");
  38                 log("         use the specified module as top module\n");
  39                 log("\n");
  40                 log("    -family <family>\n");
  41                 log("        run synthesis for the specified QuickLogic architecture\n");
  42                 log("        generate the synthesis netlist for the specified family.\n");
  43                 log("        supported values:\n");
  44                 log("        - pp3: PolarPro 3 \n");
  45                 log("\n");
  46                 log("    -blif <file>\n");
  47                 log("        write the design to the specified BLIF file. writing of an output file\n");
  48                 log("        is omitted if this parameter is not specified.\n");
  49                 log("\n");
  50                 log("    -verilog <file>\n");
  51                 log("        write the design to the specified verilog file. writing of an output file\n");
  52                 log("        is omitted if this parameter is not specified.\n");
  53                 log("\n");
  54                 log("    -abc\n");
  55                 log("        use old ABC flow, which has generally worse mapping results but is less\n");
  56                 log("        likely to have bugs.\n");
  57                 log("\n");
  58                 log("The following commands are executed by this synthesis command:\n");
  59                 help_script();
  60                 log("\n");
  61         }
  62
  63         string top_opt, blif_file, family, currmodule, verilog_file;
  64         bool abc9;
  65
  66         void clear_flags() override
  67         {
  68                 top_opt = "-auto-top";
  69                 blif_file = "";
  70                 verilog_file = "";
  71                 currmodule = "";
  72                 family = "pp3";
  73                 abc9 = true;
  74         }
  75
  76         void execute(std::vector<std::string> args, RTLIL::Design *design) override
  77         {
  78                 string run_from, run_to;
  79                 clear_flags();
  80
  81                 size_t argidx;
  82                 for (argidx = 1; argidx < args.size(); argidx++)
  83                 {
  84                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
  85                                 top_opt = "-top " + args[++argidx];
  86                                 continue;
  87                         }
  88                         if (args[argidx] == "-family" && argidx+1 < args.size()) {
  89                                 family = args[++argidx];
  90                                 continue;
  91                         }
  92                         if (args[argidx] == "-blif" && argidx+1 < args.size()) {
  93                                 blif_file = args[++argidx];
  94                                 continue;
  95                         }
  96                         if (args[argidx] == "-verilog" && argidx+1 < args.size()) {
  97                                 verilog_file = args[++argidx];
  98                                 continue;
  99                         }
 100                         if (args[argidx] == "-abc") {
 101                                 abc9 = false;
 102                                 continue;
 103                         }
 104                         break;
 105                 }
 106                 extra_args(args, argidx, design);
 107
 108                 if (!design->full_selection())
 109                         log_cmd_error("This command only operates on fully selected designs!\n");
 110
 111                 if (family != "pp3")
 112                         log_cmd_error("Invalid family specified: '%s'\n", family.c_str());
 113
 114                 if (abc9 && design->scratchpad_get_int("abc9.D", 0) == 0) {
 115                         log_warning("delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.\n");
 116                         design->scratchpad_set_int("abc9.D", 41667); // 12MHz = 83.33.. ns; divided by two to allow for interconnect delay.
 117                 }
 118
 119                 log_header(design, "Executing SYNTH_QUICKLOGIC pass.\n");
 120                 log_push();
 121
 122                 run_script(design, run_from, run_to);
 123
 124                 log_pop();
 125         }
 126
 127         void script() override
 128         {
 129                 if (check_label("begin")) {
 130                         run(stringf("read_verilog -lib -specify +/quicklogic/cells_sim.v +/quicklogic/%s_cells_sim.v", family.c_str()));
 131                         run("read_verilog -lib -specify +/quicklogic/lut_sim.v");
 132                         run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 133                 }
 134
 135                 if (check_label("coarse")) {
 136                         run("proc");
 137                         run("flatten");
 138                         run("tribuf -logic");
 139                         run("deminout");
 140                         run("opt_expr");
 141                         run("opt_clean");
 142                         run("check");
 143                         run("opt -nodffe -nosdff");
 144                         run("fsm");
 145                         run("opt");
 146                         run("wreduce");
 147                         run("peepopt");
 148                         run("opt_clean");
 149                         run("share");
 150                         run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
 151                         run("opt_expr");
 152                         run("opt_clean");
 153                         run("alumacc");
 154                         run("pmuxtree");
 155                         run("opt");
 156                         run("memory -nomap");
 157                         run("opt_clean");
 158                 }
 159
 160                 if (check_label("map_ffram")) {
 161                         run("opt -fast -mux_undef -undriven -fine");
 162                         run("memory_map -iattr -attr !ram_block -attr !rom_block -attr logic_block "
 163                                 "-attr syn_ramstyle=auto -attr syn_ramstyle=registers "
 164                                 "-attr syn_romstyle=auto -attr syn_romstyle=logic");
 165                         run("opt -undriven -fine");
 166                 }
 167
 168                 if (check_label("map_gates")) {
 169                         run("techmap");
 170                         run("opt -fast");
 171                         run("muxcover -mux8 -mux4");
 172                 }
 173
 174                 if (check_label("map_ffs")) {
 175                         run("opt_expr");
 176                         run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x");
 177
 178                         run(stringf("techmap -map +/quicklogic/%s_cells_map.v -map +/quicklogic/%s_ffs_map.v", family.c_str(), family.c_str()));
 179
 180                         run("opt_expr -mux_undef");
 181                 }
 182
 183                 if (check_label("map_luts")) {
 184                         run(stringf("techmap -map +/quicklogic/%s_latches_map.v", family.c_str()));
 185                         if (abc9) {
 186                                 run("read_verilog -lib -specify -icells +/quicklogic/abc9_model.v");
 187                                 run("techmap -map +/quicklogic/abc9_map.v");
 188                                 run("abc9 -maxlut 4 -dff");
 189                                 run("techmap -map +/quicklogic/abc9_unmap.v");
 190                         } else {
 191                                 run("abc -luts 1,2,2,4 -dress");
 192                         }
 193                         run("clean");
 194                 }
 195
 196                 if (check_label("map_cells")) {
 197                         run(stringf("techmap -map +/quicklogic/%s_lut_map.v", family.c_str()));
 198                         run("clean");
 199                 }
 200
 201                 if (check_label("check")) {
 202                         run("autoname");
 203                         run("hierarchy -check");
 204                         run("stat");
 205                         run("check -noinit");
 206                 }
 207
 208                 if (check_label("iomap")) {
 209                         run("clkbufmap -inpad ckpad Q:P");
 210                         run("iopadmap -bits -outpad outpad A:P -inpad inpad Q:P -tinoutpad bipad EN:Q:A:P A:top");
 211                 }
 212
 213                 if (check_label("finalize")) {
 214                         run("setundef -zero -params -undriven");
 215                         run("hilomap -hicell logic_1 A -locell logic_0 A -singleton A:top");
 216                         run("opt_clean -purge");
 217                         run("check");
 218                         run("blackbox =A:whitebox");
 219                 }
 220
 221                 if (check_label("blif")) {
 222                         if (!blif_file.empty() || help_mode) {
 223                                 run(stringf("write_blif -attr -param %s %s", top_opt.c_str(), blif_file.c_str()));
 224                         }
 225                 }
 226
 227                 if (check_label("verilog")) {
 228                         if (!verilog_file.empty() || help_mode) {
 229                                 run(stringf("write_verilog -noattr -nohex %s", help_mode ? "<file-name>" : verilog_file.c_str()));
 230                         }
 231                 }
 232         }
 233
 234 } SynthQuicklogicPass;
 235
 236 PRIVATE_NAMESPACE_END