Merge pull request #1397 from btut/fix/python_wrappers_inline_constructors
[yosys.git] / techlibs / xilinx / Makefile.inc
1
2 OBJS += techlibs/xilinx/synth_xilinx.o
3
4 GENFILES += techlibs/xilinx/brams_init_36.vh
5 GENFILES += techlibs/xilinx/brams_init_32.vh
6 GENFILES += techlibs/xilinx/brams_init_18.vh
7 GENFILES += techlibs/xilinx/brams_init_16.vh
8 GENFILES += techlibs/xilinx/brams_init_9.vh
9 GENFILES += techlibs/xilinx/brams_init_8.vh
10
11 EXTRA_OBJS += techlibs/xilinx/brams_init.mk
12 .SECONDARY: techlibs/xilinx/brams_init.mk
13
14 techlibs/xilinx/brams_init.mk: techlibs/xilinx/brams_init.py
15 $(Q) mkdir -p techlibs/xilinx
16 $(P) python3 $<
17 $(Q) touch $@
18
19 techlibs/xilinx/brams_init_36.vh: techlibs/xilinx/brams_init.mk
20 techlibs/xilinx/brams_init_32.vh: techlibs/xilinx/brams_init.mk
21 techlibs/xilinx/brams_init_18.vh: techlibs/xilinx/brams_init.mk
22 techlibs/xilinx/brams_init_16.vh: techlibs/xilinx/brams_init.mk
23 techlibs/xilinx/brams_init_9.vh: techlibs/xilinx/brams_init.mk
24 techlibs/xilinx/brams_init_8.vh: techlibs/xilinx/brams_init.mk
25
26 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v))
27 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v))
28 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_cells_xtra.v))
29 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6v_cells_xtra.v))
30 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_cells_xtra.v))
31 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_cells_xtra.v))
32 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams.txt))
33 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_map.v))
34 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_bb.v))
35 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams.txt))
36 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v))
37 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v))
38 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt))
39 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v))
40 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
41 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_ff_map.v))
42 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_ff_map.v))
43 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
44 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
45 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/dsp_map.v))
46
47 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_map.v))
48 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_unmap.v))
49 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_model.v))
50 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box))
51 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut))
52 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7_nowide.lut))
53
54 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
55 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
56 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_18.vh))
57 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_16.vh))
58 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_9.vh))
59 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_8.vh))
60