techlibs/xilinx/abc.box

   1 # Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
   2
   3 # F7BMUX slower than F7AMUX
   4 # Inputs: I0 I1 S0
   5 # Outputs: O
   6 F7BMUX 1 1 3 1
   7 217 223 296
   8
   9 # Inputs: I0 I1 S0
  10 # Outputs: O
  11 MUXF8 2 1 3 1
  12 104 94 273
  13
  14 # CARRY4 + CARRY4_[ABCD]X
  15 # Inputs: S0 S1 S2 S3 CYINIT DI0 DI1 DI2 DI3 CI
  16 # Outputs:  O0 O1 O2 O3 CO0 CO1 CO2 CO3
  17 #   (NB: carry chain input/output must be last input/output,
  18 #        swapped with what normally would have been the last
  19 #        output, here: CI <-> S, CO <-> O
  20 CARRY4 3 1 10 8
  21 223 -   -   -   482 -   -   -   -   222
  22 400 205 -   -   598 407 -   -   -   334
  23 523 558 226 -   584 556 537 -   -   239
  24 582 618 330 227 642 615 596 438 -   313
  25 340 -   -   -   536 379 -   -   -   271
  26 433 469 -   -   494 465 445 -   -   157
  27 512 548 292 -   592 540 520 356 -   228
  28 508 528 378 380 580 526 507 398 385 114
  29
  30 # SLICEM/A6LUT
  31 # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
  32 # Outputs: DPO SPO
  33 RAM64X1D 4 0 15 2
  34 -   -   -   -   -   -   - 124 124 124 124 124 124 - -
  35 124 124 124 124 124 124 - -   -   -   -   -   124 - -
  36
  37 # SLICEM/A6LUT + F7[AB]MUX
  38 # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
  39 # Outputs: DPO SPO
  40 RAM128X1D 5 0 17 2
  41 -   -   -   -   -   -   -   - 314 314 314 314 314 314 292 - -
  42 347 347 347 347 347 347 296 - -   -   -   -   -   -   -   - -
  43
  44 # Inputs: C CE D R
  45 # Outputs: Q
  46 FDRE 6 0 4 1
  47 - - - -
  48
  49 # Inputs: C CE D S
  50 # Outputs: Q
  51 FDSE 7 0 4 1
  52 - - - -
  53
  54 # Inputs: C CE CLR D
  55 # Outputs: Q
  56 FDCE 8 0 4 1
  57 - - 404 -
  58
  59 # Inputs: C CE D PRE
  60 # Outputs: Q
  61 FDPE 9 0 4 1
  62 - - - 404