techlibs/xilinx/abc_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *                2019  Eddie Hung    <eddie@fpgeh.com>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 // ============================================================================
  22
  23 module RAM32X1D (
  24   output DPO, SPO,
  25   input  D,
  26   input  WCLK,
  27   input  WE,
  28   input  A0, A1, A2, A3, A4,
  29   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
  30 );
  31   parameter INIT = 32'h0;
  32   parameter IS_WCLK_INVERTED = 1'b0;
  33   wire \$DPO , \$SPO ;
  34   RAM32X1D #(
  35     .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
  36   ) _TECHMAP_REPLACE_ (
  37     .DPO(\$DPO ), .SPO(\$SPO ),
  38     .D(D), .WCLK(WCLK), .WE(WE),
  39     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
  40     .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
  41   );
  42   \$__ABC_LUT6 dpo (.A(\$DPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(DPO));
  43   \$__ABC_LUT6 spo (.A(\$SPO ), .S({1'b0, A0, A1, A2, A3, A4}), .Y(SPO));
  44 endmodule
  45
  46 module RAM64X1D (
  47   output DPO, SPO,
  48   input  D,
  49   input  WCLK,
  50   input  WE,
  51   input  A0, A1, A2, A3, A4, A5,
  52   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
  53 );
  54   parameter INIT = 64'h0;
  55   parameter IS_WCLK_INVERTED = 1'b0;
  56   wire \$DPO , \$SPO ;
  57   RAM64X1D #(
  58     .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
  59   ) _TECHMAP_REPLACE_ (
  60     .DPO(\$DPO ), .SPO(\$SPO ),
  61     .D(D), .WCLK(WCLK), .WE(WE),
  62     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
  63     .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
  64   );
  65   \$__ABC_LUT6 dpo (.A(\$DPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(DPO));
  66   \$__ABC_LUT6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
  67 endmodule
  68
  69 module RAM128X1D (
  70   output       DPO, SPO,
  71   input        D,
  72   input        WCLK,
  73   input        WE,
  74   input  [6:0] A, DPRA
  75 );
  76   parameter INIT = 128'h0;
  77   parameter IS_WCLK_INVERTED = 1'b0;
  78   wire \$DPO , \$SPO ;
  79   RAM128X1D #(
  80     .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
  81   ) _TECHMAP_REPLACE_ (
  82     .DPO(\$DPO ), .SPO(\$SPO ),
  83     .D(D), .WCLK(WCLK), .WE(WE),
  84     .A(A),
  85     .DPRA(DPRA)
  86   );
  87   \$__ABC_LUT7 dpo (.A(\$DPO ), .S(A), .Y(DPO));
  88   \$__ABC_LUT7 spo (.A(\$SPO ), .S(A), .Y(SPO));
  89 endmodule
  90
  91 module SRL16E (
  92   output Q,
  93   input A0, A1, A2, A3, CE, CLK, D
  94 );
  95   parameter [15:0] INIT = 16'h0000;
  96   parameter [0:0] IS_CLK_INVERTED = 1'b0;
  97   wire \$Q ;
  98   SRL16E #(
  99     .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
 100   ) _TECHMAP_REPLACE_ (
 101     .Q(\$Q ),
 102     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
 103   );
 104   \$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A0, A1, A2, A3, 1'b1}), .Y(Q));
 105 endmodule
 106
 107 module SRLC32E (
 108   output Q,
 109   output Q31,
 110   input [4:0] A,
 111   input CE, CLK, D
 112 );
 113   parameter [31:0] INIT = 32'h00000000;
 114   parameter [0:0] IS_CLK_INVERTED = 1'b0;
 115   wire \$Q ;
 116   SRLC32E #(
 117     .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
 118   ) _TECHMAP_REPLACE_ (
 119     .Q(\$Q ), .Q31(Q31),
 120     .A(A), .CE(CE), .CLK(CLK), .D(D)
 121   );
 122   \$__ABC_LUT6 q (.A(\$Q ), .S({1'b1, A}), .Y(Q));
 123 endmodule