2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 // ============================================================================
23 (* abc_box_id = 3, lib_whitebox *)
24 module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
25 assign O = S1 ? (S0 ? I3 : I2)
29 module \$__ABC_FF_ (input C, D, output Q);
32 (* abc_box_id = 1000 *)
33 module \$__ABC_ASYNC (input A, S, output Y);
36 (* abc_box_id=1001, lib_whitebox, abc_flop *)
37 module \$__ABC_FDRE ((* abc_flop_q, abc_arrival=303 *) output Q,
38 (* abc_flop_clk *) input C,
39 (* abc_flop_en *) input CE,
40 (* abc_flop_d *) input D,
42 parameter [0:0] INIT = 1'b0;
43 parameter [0:0] IS_C_INVERTED = 1'b0;
44 parameter [0:0] IS_D_INVERTED = 1'b0;
45 parameter [0:0] IS_R_INVERTED = 1'b0;
46 parameter CLK_POLARITY = !IS_C_INVERTED;
47 parameter EN_POLARITY = 1'b1;
48 assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
51 (* abc_box_id=1002, lib_whitebox, abc_flop *)
52 module \$__ABC_FDRE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
53 (* abc_flop_clk *) input C,
54 (* abc_flop_en *) input CE,
55 (* abc_flop_d *) input D,
57 parameter [0:0] INIT = 1'b0;
58 parameter CLK_POLARITY = 1'b0;
59 parameter EN_POLARITY = 1'b1;
60 assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
63 (* abc_box_id=1003, lib_whitebox, abc_flop *)
64 module \$__ABC_FDCE ((* abc_flop_q, abc_arrival=303 *) output Q,
65 (* abc_flop_clk *) input C,
66 (* abc_flop_en *) input CE,
67 (* abc_flop_d *) input D,
69 parameter [0:0] INIT = 1'b0;
70 parameter [0:0] IS_C_INVERTED = 1'b0;
71 parameter [0:0] IS_D_INVERTED = 1'b0;
72 parameter [0:0] IS_CLR_INVERTED = 1'b0;
73 parameter CLK_POLARITY = !IS_C_INVERTED;
74 parameter EN_POLARITY = 1'b1;
75 assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
78 (* abc_box_id=1004, lib_whitebox, abc_flop *)
79 module \$__ABC_FDCE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
80 (* abc_flop_clk *) input C,
81 (* abc_flop_en *) input CE,
82 (* abc_flop_d *) input D,
84 parameter [0:0] INIT = 1'b0;
85 parameter CLK_POLARITY = 1'b0;
86 parameter EN_POLARITY = 1'b1;
87 assign Q = (CE && !CLR) ? D : \$pastQ ;
90 (* abc_box_id=1005, lib_whitebox, abc_flop *)
91 module \$__ABC_FDPE ((* abc_flop_q, abc_arrival=303 *) output Q,
92 (* abc_flop_clk *) input C,
93 (* abc_flop_en *) input CE,
94 (* abc_flop_d *) input D,
96 parameter [0:0] INIT = 1'b0;
97 parameter [0:0] IS_C_INVERTED = 1'b0;
98 parameter [0:0] IS_D_INVERTED = 1'b0;
99 parameter [0:0] IS_PRE_INVERTED = 1'b0;
100 parameter CLK_POLARITY = !IS_C_INVERTED;
101 parameter EN_POLARITY = 1'b1;
102 assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
105 (* abc_box_id=1006, lib_whitebox, abc_flop *)
106 module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
107 (* abc_flop_clk *) input C,
108 (* abc_flop_en *) input CE,
109 (* abc_flop_d *) input D,
110 input PRE, \$pastQ );
111 parameter [0:0] INIT = 1'b0;
112 parameter CLK_POLARITY = 1'b0;
113 parameter EN_POLARITY = 1'b1;
114 assign Q = (CE && !PRE) ? D : \$pastQ ;
117 module \$__XILINX_MUXF78 (O, I0, I1, I2, I3, S0, S1);
119 input I0, I1, I2, I3, S0, S1;
121 parameter _TECHMAP_BITS_CONNMAP_ = 0;
122 parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I0_ = 0;
123 parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I1_ = 0;
124 parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I2_ = 0;
125 parameter [_TECHMAP_BITS_CONNMAP_-1:0] _TECHMAP_CONNMAP_I3_ = 0;
126 parameter _TECHMAP_CONSTMSK_S0_ = 0;
127 parameter _TECHMAP_CONSTVAL_S0_ = 0;
128 parameter _TECHMAP_CONSTMSK_S1_ = 0;
129 parameter _TECHMAP_CONSTVAL_S1_ = 0;
130 if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
132 else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_)
135 MUXF7 mux7a (.I0(I0), .I1(I1), .S(S0), .O(T0));
136 if (_TECHMAP_CONSTMSK_S0_ && _TECHMAP_CONSTVAL_S0_ === 1'b1)
138 else if (_TECHMAP_CONSTMSK_S0_ || _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_)
141 MUXF7 mux7b (.I0(I2), .I1(I3), .S(S0), .O(T1));
142 if (_TECHMAP_CONSTMSK_S1_ && _TECHMAP_CONSTVAL_S1_ === 1'b1)
144 else if (_TECHMAP_CONSTMSK_S1_ || (_TECHMAP_CONNMAP_I0_ === _TECHMAP_CONNMAP_I1_ && _TECHMAP_CONNMAP_I1_ === _TECHMAP_CONNMAP_I2_ && _TECHMAP_CONNMAP_I2_ === _TECHMAP_CONNMAP_I3_))
147 MUXF8 mux8 (.I0(T0), .I1(T1), .S(S1), .O(O));