techlibs/xilinx/abc_model.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *                2019  Eddie Hung    <eddie@fpgeh.com>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 // ============================================================================
  22
  23 // Box containing MUXF7.[AB] + MUXF8,
  24 //   Necessary to make these an atomic unit so that
  25 //   ABC cannot optimise just one of the MUXF7 away
  26 //   and expect to save on its delay
  27 (* abc_box_id = 3, lib_whitebox *)
  28 module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
  29   assign O = S1 ? (S0 ? I3 : I2)
  30                 : (S0 ? I1 : I0);
  31 endmodule
  32
  33 // Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
  34 //   Necessary since RAMD* and SRL* have both combinatorial (i.e.
  35 //   same-cycle read operation) and sequential (write operation
  36 //   is only committed on the next clock edge).
  37 //   To model the combinatorial path, such cells have to be split
  38 //   into comb and seq parts, with this box modelling only the former.
  39 (* abc_box_id=2000 *)
  40 module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
  41 endmodule
  42 // Box to emulate comb/seq behaviour of RAMD128
  43 (* abc_box_id=2001 *)
  44 module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
  45 endmodule
  46
  47 `define ABC_DSP48E1(__NAME__) """
  48 module \$__ABC_DSP48E1_MULT (
  49     output [29:0] ACOUT,
  50     output [17:0] BCOUT,
  51     output reg CARRYCASCOUT,
  52     output reg [3:0] CARRYOUT,
  53     output reg MULTSIGNOUT,
  54     output OVERFLOW,
  55     output reg signed [47:0] P,
  56     output PATTERNBDETECT,
  57     output PATTERNDETECT,
  58     output [47:0] PCOUT,
  59     output UNDERFLOW,
  60     input signed [29:0] A,
  61     input [29:0] ACIN,
  62     input [3:0] ALUMODE,
  63     input signed [17:0] B,
  64     input [17:0] BCIN,
  65     input [47:0] C,
  66     input CARRYCASCIN,
  67     input CARRYIN,
  68     input [2:0] CARRYINSEL,
  69     input CEA1,
  70     input CEA2,
  71     input CEAD,
  72     input CEALUMODE,
  73     input CEB1,
  74     input CEB2,
  75     input CEC,
  76     input CECARRYIN,
  77     input CECTRL,
  78     input CED,
  79     input CEINMODE,
  80     input CEM,
  81     input CEP,
  82     input CLK,
  83     input [24:0] D,
  84     input [4:0] INMODE,
  85     input MULTSIGNIN,
  86     input [6:0] OPMODE,
  87     input [47:0] PCIN,
  88     input RSTA,
  89     input RSTALLCARRYIN,
  90     input RSTALUMODE,
  91     input RSTB,
  92     input RSTC,
  93     input RSTCTRL,
  94     input RSTD,
  95     input RSTINMODE,
  96     input RSTM,
  97     input RSTP
  98 );
  99     parameter integer ACASCREG = 1;
 100     parameter integer ADREG = 1;
 101     parameter integer ALUMODEREG = 1;
 102     parameter integer AREG = 1;
 103     parameter AUTORESET_PATDET = "NO_RESET";
 104     parameter A_INPUT = "DIRECT";
 105     parameter integer BCASCREG = 1;
 106     parameter integer BREG = 1;
 107     parameter B_INPUT = "DIRECT";
 108     parameter integer CARRYINREG = 1;
 109     parameter integer CARRYINSELREG = 1;
 110     parameter integer CREG = 1;
 111     parameter integer DREG = 1;
 112     parameter integer INMODEREG = 1;
 113     parameter integer MREG = 1;
 114     parameter integer OPMODEREG = 1;
 115     parameter integer PREG = 1;
 116     parameter SEL_MASK = "MASK";
 117     parameter SEL_PATTERN = "PATTERN";
 118     parameter USE_DPORT = "FALSE";
 119     parameter USE_MULT = "MULTIPLY";
 120     parameter USE_PATTERN_DETECT = "NO_PATDET";
 121     parameter USE_SIMD = "ONE48";
 122     parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
 123     parameter [47:0] PATTERN = 48'h000000000000;
 124     parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
 125     parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
 126     parameter [0:0] IS_CLK_INVERTED = 1'b0;
 127     parameter [4:0] IS_INMODE_INVERTED = 5'b0;
 128     parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
 129 endmodule
 130 """
 131 (* abc_box_id=3000 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT )
 132 (* abc_box_id=3001 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT_DPORT )
 133 (* abc_box_id=3002 *) `ABC_DSP48E1(\$__ABC_DSP48E1 )
 134
 135
 136 // Modules used to model the comb/seq behaviour of DSP48E1
 137 //   With abc_map.v responsible for splicing the below modules
 138 //   into between the combinatorial DSP48E1 box (e.g. disconnecting
 139 //   A when AREG, MREG or PREG is enabled and splicing in the
 140 //   "$__ABC_DSP48E1_MULT_AREG" blackbox as "REG" in the diagram
 141 //   below) this acts to first disables the combinatorial path
 142 //   (as there is no connectivity through REG), and secondly,
 143 //   since this is blackbox a new PI will be introduced, one which
 144 //   will have the relevant arrival time (corresponding to delay from
 145 //   AREG to P) attached.
 146 //   Note: Since these "$__ABC_DSP48E1*_*REG" modules are of a
 147 //   sequential nature, they are not passed as a box to ABC./
 148 //
 149 //   On the other hand, the "$__ABC_DSP48E1_MUX" is a combinatorial
 150 //   blackbox that is passed to ABC, with zero delay.
 151 //
 152 //   Doing so should means that ABC is able to analyse the
 153 //   worst-case delay through to P, regardless of if it was
 154 //   through any combinatorial paths (e.g. B, below) or an
 155 //   internal register (A2REG).
 156 //   However, the true value of being as complete as this is
 157 //   questionable since if AREG=1 and BREG=0 (as below)
 158 //   then the worse-case path would very likely be through B
 159 //   and very unlikely to be through AREG.Q...?
 160 //
 161 //   In graphical form:
 162 //
 163 //                 +-----+
 164 //         +-------| REG |-----+
 165 //         |       +-----+     |
 166 //         |                   |
 167 //         |    +---------+    |   __
 168 //    A >>-+X X-|         |    +--|  \
 169 //              | DSP48E1 |P      | M |--->> P
 170 //              | AREG=1  |-------|__/
 171 //    B >>------|         |
 172 //              +---------+
 173 //
 174
 175 (* abc_box_id=2100 *)
 176 module \$__ABC_DSP48E1_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O);
 177 endmodule
 178
 179 module $__ABC_DSP48E1_MULT_AREG (input [29:0] I, output [29:0] O, (* abc_arrival=2952 *) output P, (* abc_arrival=3098 *) output PCOUT); endmodule
 180 module $__ABC_DSP48E1_MULT_BREG (input [17:0] I, output [17:0] O, (* abc_arrival=2813 *) output P, (* abc_arrival=2960 *) output PCOUT); endmodule
 181 module $__ABC_DSP48E1_MULT_CREG (input [47:0] I, output [47:0] O, (* abc_arrival=1687 *) output P, (* abc_arrival=1835 *) output PCOUT); endmodule
 182 module $__ABC_DSP48E1_MULT_MREG (input [47:0] I, output [47:0] O, (* abc_arrival=1671 *) output P, (* abc_arrival=1819 *) output PCOUT); endmodule
 183 module $__ABC_DSP48E1_MULT_PREG (input [47:0] I, output [47:0] O, (* abc_arrival= 329 *) output P, (* abc_arrival= 435 *) output PCOUT); endmodule
 184
 185 module $__ABC_DSP48E1_MULT_DPORT_AREG  (input [29:0] I, output [29:0] O, (* abc_arrival=3935 *) output P, (* abc_arrival=4083 *) output PCOUT); endmodule
 186 module $__ABC_DSP48E1_MULT_DPORT_BREG  (input [17:0] I, output [17:0] O, (* abc_arrival=2813 *) output P, (* abc_arrival=2960 *) output PCOUT); endmodule
 187 module $__ABC_DSP48E1_MULT_DPORT_CREG  (input [47:0] I, output [47:0] O, (* abc_arrival=1687 *) output P, (* abc_arrival=1835 *) output PCOUT); endmodule
 188 module $__ABC_DSP48E1_MULT_DPORT_DREG  (input [47:0] I, output [47:0] O, (* abc_arrival=3908 *) output P, (* abc_arrival=4056 *) output PCOUT); endmodule
 189 module $__ABC_DSP48E1_MULT_DPORT_ADREG (input [47:0] I, output [47:0] O, (* abc_arrival=2958 *) output P, (* abc_arrival=2859 *) output PCOUT); endmodule
 190 module $__ABC_DSP48E1_MULT_DPORT_MREG  (input [47:0] I, output [47:0] O, (* abc_arrival=1671 *) output P, (* abc_arrival=1819 *) output PCOUT); endmodule
 191 module $__ABC_DSP48E1_MULT_DPORT_PREG  (input [47:0] I, output [47:0] O, (* abc_arrival= 329 *) output P, (* abc_arrival= 435 *) output PCOUT); endmodule
 192
 193 module $__ABC_DSP48E1_AREG (input [29:0] I, output [29:0] O, (* abc_arrival=1632 *) output P, (* abc_arrival=1780 *) output PCOUT); endmodule
 194 module $__ABC_DSP48E1_BREG (input [17:0] I, output [17:0] O, (* abc_arrival=1616 *) output P, (* abc_arrival=1765 *) output PCOUT); endmodule
 195 module $__ABC_DSP48E1_CREG (input [47:0] I, output [47:0] O, (* abc_arrival=1687 *) output P, (* abc_arrival=1835 *) output PCOUT); endmodule
 196 module $__ABC_DSP48E1_PREG (input [47:0] I, output [47:0] O, (* abc_arrival= 329 *) output P, (* abc_arrival= 435 *) output PCOUT); endmodule