techlibs/xilinx/abc_model.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *                2019  Eddie Hung    <eddie@fpgeh.com>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 // ============================================================================
  22
  23 // Box containing MUXF7.[AB] + MUXF8,
  24 //   Necessary to make these an atomic unit so that
  25 //   ABC cannot optimise just one of the MUXF7 away
  26 //   and expect to save on its delay
  27 (* abc_box_id = 3, lib_whitebox *)
  28 module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
  29   assign O = S1 ? (S0 ? I3 : I2)
  30                 : (S0 ? I1 : I0);
  31 endmodule
  32
  33 // Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
  34 //   Necessary since RAMD* and SRL* have both combinatorial (i.e.
  35 //   same-cycle read operation) and sequential (write operation
  36 //   is only committed on the next clock edge).
  37 //   To model the combinatorial path, such cells have to be split
  38 //   into comb and seq parts, with this box modelling only the former.
  39 (* abc_box_id=2000 *)
  40 module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
  41 endmodule
  42 // Box to emulate comb/seq behaviour of RAMD128
  43 (* abc_box_id=2001 *)
  44 module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
  45 endmodule
  46
  47
  48 // Modules used to model the comb/seq behaviour of DSP48E1
  49 //   With abc_map.v responsible for splicing the below modules
  50 //   between the combinatorial DSP48E1 box (e.g. disconnecting
  51 //   A when AREG, MREG or PREG is enabled and splicing in the
  52 //   "$__ABC_DSP48E1_REG" blackbox as "REG" in the diagram below)
  53 //   this acts to first disables the combinatorial path (as there
  54 //   is no connectivity through REG), and secondly, since this is
  55 //   blackbox a new PI will be introduced with an arrival time of
  56 //   zero.
  57 //   Note: Since these "$__ABC_DSP48E1_REG" modules are of a
  58 //   sequential nature, they are not passed as a box to ABC and
  59 //   (desirably) represented as PO/PIs.
  60 //
  61 //   At the DSP output, we place a blackbox mux ("M" in the diagram
  62 //   below) to capture the fact that the critical-path could come
  63 //   from any one of its inputs.
  64 //   In contrast to "REG", the "$__ABC_DSP48E1_*_MUX" modules are
  65 //   combinatorial blackboxes that do get passed to ABC.
  66 //   The propagation delay through this box (specified in the box
  67 //   file) captures the arrival time of the register (i.e.
  68 //   propagation from AREG to P after clock edge), or zero delay
  69 //   for the combinatorial path from the DSP.
  70 //
  71 //   Doing so should means that ABC is able to analyse the
  72 //   worst-case delay through to P, regardless of if it was
  73 //   through any combinatorial paths (e.g. B, below) or an
  74 //   internal register (A2REG).
  75 //   However, the true value of being as complete as this is
  76 //   questionable since if AREG=1 and BREG=0 (as below)
  77 //   then the worse-case path would very likely be through B
  78 //   and very unlikely to be through AREG.Q...?
  79 //
  80 //   In graphical form:
  81 //
  82 //                 +-----+
  83 //         +------>> REG >>----+
  84 //         |       +-----+     |
  85 //         |                   |
  86 //         |    +---------+    |   __
  87 //    A >>-+X X-|         |    +--|  \
  88 //              | DSP48E1 |P      | M |--->> P
  89 //              | AREG=1  |-------|__/
  90 //    B >>------|         |
  91 //              +---------+
  92 //
  93 `define ABC_DSP48E1_MUX(__NAME__) """
  94 module __NAME__ (input Aq, ADq, Bq, Cq, Dq, input [47:0] I, input Mq, input [47:0] P, input Pq, output [47:0] O);
  95 endmodule
  96 """
  97 (* abc_box_id=2100 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_P_MUX )
  98 (* abc_box_id=2101 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_PCOUT_MUX )
  99 (* abc_box_id=2102 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_P_MUX )
 100 (* abc_box_id=2103 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX )
 101 (* abc_box_id=2104 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_P_MUX )
 102 (* abc_box_id=2105 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_PCOUT_MUX )
 103
 104 `define ABC_DSP48E1(__NAME__) """
 105 module \$__ABC_DSP48E1_MULT (
 106     output [29:0] ACOUT,
 107     output [17:0] BCOUT,
 108     output reg CARRYCASCOUT,
 109     output reg [3:0] CARRYOUT,
 110     output reg MULTSIGNOUT,
 111     output OVERFLOW,
 112     output reg signed [47:0] P,
 113     output PATTERNBDETECT,
 114     output PATTERNDETECT,
 115     output [47:0] PCOUT,
 116     output UNDERFLOW,
 117     input signed [29:0] A,
 118     input [29:0] ACIN,
 119     input [3:0] ALUMODE,
 120     input signed [17:0] B,
 121     input [17:0] BCIN,
 122     input [47:0] C,
 123     input CARRYCASCIN,
 124     input CARRYIN,
 125     input [2:0] CARRYINSEL,
 126     input CEA1,
 127     input CEA2,
 128     input CEAD,
 129     input CEALUMODE,
 130     input CEB1,
 131     input CEB2,
 132     input CEC,
 133     input CECARRYIN,
 134     input CECTRL,
 135     input CED,
 136     input CEINMODE,
 137     input CEM,
 138     input CEP,
 139     input CLK,
 140     input [24:0] D,
 141     input [4:0] INMODE,
 142     input MULTSIGNIN,
 143     input [6:0] OPMODE,
 144     input [47:0] PCIN,
 145     input RSTA,
 146     input RSTALLCARRYIN,
 147     input RSTALUMODE,
 148     input RSTB,
 149     input RSTC,
 150     input RSTCTRL,
 151     input RSTD,
 152     input RSTINMODE,
 153     input RSTM,
 154     input RSTP
 155 );
 156     parameter integer ACASCREG = 1;
 157     parameter integer ADREG = 1;
 158     parameter integer ALUMODEREG = 1;
 159     parameter integer AREG = 1;
 160     parameter AUTORESET_PATDET = "NO_RESET";
 161     parameter A_INPUT = "DIRECT";
 162     parameter integer BCASCREG = 1;
 163     parameter integer BREG = 1;
 164     parameter B_INPUT = "DIRECT";
 165     parameter integer CARRYINREG = 1;
 166     parameter integer CARRYINSELREG = 1;
 167     parameter integer CREG = 1;
 168     parameter integer DREG = 1;
 169     parameter integer INMODEREG = 1;
 170     parameter integer MREG = 1;
 171     parameter integer OPMODEREG = 1;
 172     parameter integer PREG = 1;
 173     parameter SEL_MASK = "MASK";
 174     parameter SEL_PATTERN = "PATTERN";
 175     parameter USE_DPORT = "FALSE";
 176     parameter USE_MULT = "MULTIPLY";
 177     parameter USE_PATTERN_DETECT = "NO_PATDET";
 178     parameter USE_SIMD = "ONE48";
 179     parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
 180     parameter [47:0] PATTERN = 48'h000000000000;
 181     parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
 182     parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
 183     parameter [0:0] IS_CLK_INVERTED = 1'b0;
 184     parameter [4:0] IS_INMODE_INVERTED = 5'b0;
 185     parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
 186 endmodule
 187 """
 188 (* abc_box_id=3000 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT )
 189 (* abc_box_id=3001 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT_DPORT )
 190 (* abc_box_id=3002 *) `ABC_DSP48E1(\$__ABC_DSP48E1 )