techlibs/xilinx/abc_model.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *                2019  Eddie Hung    <eddie@fpgeh.com>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 // ============================================================================
  22
  23 (* abc_box_id = 3, lib_whitebox *)
  24 module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
  25   assign O = S1 ? (S0 ? I3 : I2)
  26                 : (S0 ? I1 : I0);
  27 endmodule
  28
  29 (* abc_box_id=2000 *)
  30 module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
  31 endmodule
  32 (* abc_box_id=2001 *)
  33 module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
  34 endmodule