techlibs/xilinx/abc_model.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *                2019  Eddie Hung    <eddie@fpgeh.com>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 // ============================================================================
  22
  23 // Box containing MUXF7.[AB] + MUXF8,
  24 //   Necessary to make these an atomic unit so that
  25 //   ABC cannot optimise just one of the MUXF7 away
  26 //   and expect to save on its delay
  27 (* abc_box_id = 3, lib_whitebox *)
  28 module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
  29   assign O = S1 ? (S0 ? I3 : I2)
  30                 : (S0 ? I1 : I0);
  31 endmodule
  32
  33 // Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
  34 //   Necessary since RAMD* and SRL* have both combinatorial (i.e.
  35 //   same-cycle read operation) and sequential (write operation
  36 //   is only committed on the next clock edge).
  37 //   To model the combinatorial path, such cells have to be split
  38 //   into comb and seq parts, with this box modelling only the former.
  39 (* abc_box_id=2000 *)
  40 module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
  41 endmodule
  42 // Box to emulate comb/seq behaviour of RAMD128
  43 (* abc_box_id=2001 *)
  44 module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
  45 endmodule
  46
  47 // Boxes used to represent the comb/seq behaviour of DSP48E1
  48 //   With abc_map.v responsible for disconnecting inputs to
  49 //   the combinatorial DSP48E1 model by a register (e.g.
  50 //   disconnecting A when AREG, MREG or PREG is enabled)
  51 //   this blackbox captures the existence of a replacement
  52 //   path between AREG/BREG/CREG/etc. and P/PCOUT.
  53 //   Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at
  54 //   the box at zero time, the combinatorial delay through
  55 //   these muxes thus represents the clock-to-q delay at
  56 //   P/PCOUT.
  57 //   Doing so should means that ABC is able to analyse the
  58 //   worst-case delay through to P.
  59 //   However, the true value of being as complete as this is
  60 //   questionable since if AREG=1 and BREG=0 (as below)
  61 //   then the worse-case path would very likely be through B
  62 //   and very unlikely to be through AREG.Q...?
  63 //
  64 //   In graphical form:
  65 //
  66 //             NEW "PI" >>---+
  67 //           for AREG.Q      |
  68 //                           |
  69 //            +---------+    |   __
  70 //    A --X X-|         |    +--|  \
  71 //            | DSP48E1 |P      |   |--- P
  72 //            | AREG=1  |-------|__/
  73 //    B ------|         |
  74 //            +---------+
  75 //
  76 (* abc_box_id=2100 *)
  77 module \$__ABC_DSP48E1_MULT_P_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O);
  78 endmodule
  79 (* abc_box_id=2101 *)
  80 module \$__ABC_DSP48E1_MULT_PCOUT_MUX (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O);
  81 endmodule
  82
  83 (* abc_box_id=3000 *)
  84 module \$__ABC_DSP48E1_MULT (
  85     output [29:0] ACOUT,
  86     output [17:0] BCOUT,
  87     output reg CARRYCASCOUT,
  88     output reg [3:0] CARRYOUT,
  89     output reg MULTSIGNOUT,
  90     output OVERFLOW,
  91     output reg signed [47:0] P,
  92     output PATTERNBDETECT,
  93     output PATTERNDETECT,
  94     output [47:0] PCOUT,
  95     output UNDERFLOW,
  96     input signed [29:0] A,
  97     input [29:0] ACIN,
  98     input [3:0] ALUMODE,
  99     input signed [17:0] B,
 100     input [17:0] BCIN,
 101     input [47:0] C,
 102     input CARRYCASCIN,
 103     input CARRYIN,
 104     input [2:0] CARRYINSEL,
 105     input CEA1,
 106     input CEA2,
 107     input CEAD,
 108     input CEALUMODE,
 109     input CEB1,
 110     input CEB2,
 111     input CEC,
 112     input CECARRYIN,
 113     input CECTRL,
 114     input CED,
 115     input CEINMODE,
 116     input CEM,
 117     input CEP,
 118     input CLK,
 119     input [24:0] D,
 120     input [4:0] INMODE,
 121     input MULTSIGNIN,
 122     input [6:0] OPMODE,
 123     input [47:0] PCIN,
 124     input RSTA,
 125     input RSTALLCARRYIN,
 126     input RSTALUMODE,
 127     input RSTB,
 128     input RSTC,
 129     input RSTCTRL,
 130     input RSTD,
 131     input RSTINMODE,
 132     input RSTM,
 133     input RSTP
 134 );
 135     parameter integer ACASCREG = 1;
 136     parameter integer ADREG = 1;
 137     parameter integer ALUMODEREG = 1;
 138     parameter integer AREG = 1;
 139     parameter AUTORESET_PATDET = "NO_RESET";
 140     parameter A_INPUT = "DIRECT";
 141     parameter integer BCASCREG = 1;
 142     parameter integer BREG = 1;
 143     parameter B_INPUT = "DIRECT";
 144     parameter integer CARRYINREG = 1;
 145     parameter integer CARRYINSELREG = 1;
 146     parameter integer CREG = 1;
 147     parameter integer DREG = 1;
 148     parameter integer INMODEREG = 1;
 149     parameter integer MREG = 1;
 150     parameter integer OPMODEREG = 1;
 151     parameter integer PREG = 1;
 152     parameter SEL_MASK = "MASK";
 153     parameter SEL_PATTERN = "PATTERN";
 154     parameter USE_DPORT = "FALSE";
 155     parameter USE_MULT = "MULTIPLY";
 156     parameter USE_PATTERN_DETECT = "NO_PATDET";
 157     parameter USE_SIMD = "ONE48";
 158     parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
 159     parameter [47:0] PATTERN = 48'h000000000000;
 160     parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
 161     parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
 162     parameter [0:0] IS_CLK_INVERTED = 1'b0;
 163     parameter [4:0] IS_INMODE_INVERTED = 5'b0;
 164     parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
 165 endmodule
 166
 167