techlibs/xilinx/abc_model.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *                2019  Eddie Hung    <eddie@fpgeh.com>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 // ============================================================================
  22
  23 // Box containing MUXF7.[AB] + MUXF8,
  24 //   Necessary to make these an atomic unit so that
  25 //   ABC cannot optimise just one of the MUXF7 away
  26 //   and expect to save on its delay
  27 (* abc_box_id = 3, lib_whitebox *)
  28 module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
  29   assign O = S1 ? (S0 ? I3 : I2)
  30                 : (S0 ? I1 : I0);
  31 endmodule
  32
  33 // Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
  34 //   Necessary since RAMD* and SRL* have both combinatorial (i.e.
  35 //   same-cycle read operation) and sequential (write operation
  36 //   is only committed on the next clock edge).
  37 //   To model the combinatorial path, such cells have to be split
  38 //   into comb and seq parts, with this box modelling only the former.
  39 (* abc_box_id=2000 *)
  40 module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
  41 endmodule
  42 // Box to emulate comb/seq behaviour of RAMD128
  43 (* abc_box_id=2001 *)
  44 module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
  45 endmodule
  46
  47 // Boxes used to represent the comb/seq behaviour of DSP48E1
  48 //   With abc_map.v responsible for disconnecting inputs to
  49 //   the combinatorial DSP48E1 model by a register (e.g.
  50 //   disconnecting A when AREG, MREG or PREG is enabled)
  51 //   this blackbox captures the existence of a replacement
  52 //   path between AREG/BREG/CREG/etc. and P/PCOUT.
  53 //   Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at
  54 //   the box at zero time, the combinatorial delay through
  55 //   these boxes thus represents the clock-to-q delay
  56 //   (arrival time) at P/PCOUT.
  57 //   Doing so should means that ABC is able to analyse the
  58 //   worst-case delay through to P, regardless of if it was
  59 //   through any combinatorial paths (e.g. B, below) or an
  60 //   internal register (A2REG).
  61 //   However, the true value of being as complete as this is
  62 //   questionable since if AREG=1 and BREG=0 (as below)
  63 //   then the worse-case path would very likely be through B
  64 //   and very unlikely to be through AREG.Q...?
  65 //
  66 //   In graphical form:
  67 //
  68 //               NEW "PI" >>---+
  69 //             for AREG.Q      |
  70 //                             |
  71 //              +---------+    |   __
  72 //    A >>--X X-|         |    +--|  \
  73 //              | DSP48E1 |P      |   |--->> P
  74 //              | AREG=1  |-------|__/
  75 //    B >>------|         |
  76 //              +---------+
  77 //
  78 `define ABC_DSP48E1_MUX(__NAME__) """
  79 module __NAME__ (input Aq, ADq, Bq, Cq, Dq, Mq, input [47:0] P, input Pq, output [47:0] O);
  80 endmodule
  81 """
  82 (* abc_box_id=2100 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_P_MUX )
  83 (* abc_box_id=2101 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_PCOUT_MUX )
  84 (* abc_box_id=2102 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_P_MUX )
  85 (* abc_box_id=2103 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX )
  86 (* abc_box_id=2104 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_P_MUX )
  87 (* abc_box_id=2105 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_PCOUT_MUX )
  88
  89 `define ABC_DSP48E1(__NAME__) """
  90 module \$__ABC_DSP48E1_MULT (
  91     output [29:0] ACOUT,
  92     output [17:0] BCOUT,
  93     output reg CARRYCASCOUT,
  94     output reg [3:0] CARRYOUT,
  95     output reg MULTSIGNOUT,
  96     output OVERFLOW,
  97     output reg signed [47:0] P,
  98     output PATTERNBDETECT,
  99     output PATTERNDETECT,
 100     output [47:0] PCOUT,
 101     output UNDERFLOW,
 102     input signed [29:0] A,
 103     input [29:0] ACIN,
 104     input [3:0] ALUMODE,
 105     input signed [17:0] B,
 106     input [17:0] BCIN,
 107     input [47:0] C,
 108     input CARRYCASCIN,
 109     input CARRYIN,
 110     input [2:0] CARRYINSEL,
 111     input CEA1,
 112     input CEA2,
 113     input CEAD,
 114     input CEALUMODE,
 115     input CEB1,
 116     input CEB2,
 117     input CEC,
 118     input CECARRYIN,
 119     input CECTRL,
 120     input CED,
 121     input CEINMODE,
 122     input CEM,
 123     input CEP,
 124     input CLK,
 125     input [24:0] D,
 126     input [4:0] INMODE,
 127     input MULTSIGNIN,
 128     input [6:0] OPMODE,
 129     input [47:0] PCIN,
 130     input RSTA,
 131     input RSTALLCARRYIN,
 132     input RSTALUMODE,
 133     input RSTB,
 134     input RSTC,
 135     input RSTCTRL,
 136     input RSTD,
 137     input RSTINMODE,
 138     input RSTM,
 139     input RSTP
 140 );
 141     parameter integer ACASCREG = 1;
 142     parameter integer ADREG = 1;
 143     parameter integer ALUMODEREG = 1;
 144     parameter integer AREG = 1;
 145     parameter AUTORESET_PATDET = "NO_RESET";
 146     parameter A_INPUT = "DIRECT";
 147     parameter integer BCASCREG = 1;
 148     parameter integer BREG = 1;
 149     parameter B_INPUT = "DIRECT";
 150     parameter integer CARRYINREG = 1;
 151     parameter integer CARRYINSELREG = 1;
 152     parameter integer CREG = 1;
 153     parameter integer DREG = 1;
 154     parameter integer INMODEREG = 1;
 155     parameter integer MREG = 1;
 156     parameter integer OPMODEREG = 1;
 157     parameter integer PREG = 1;
 158     parameter SEL_MASK = "MASK";
 159     parameter SEL_PATTERN = "PATTERN";
 160     parameter USE_DPORT = "FALSE";
 161     parameter USE_MULT = "MULTIPLY";
 162     parameter USE_PATTERN_DETECT = "NO_PATDET";
 163     parameter USE_SIMD = "ONE48";
 164     parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
 165     parameter [47:0] PATTERN = 48'h000000000000;
 166     parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
 167     parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
 168     parameter [0:0] IS_CLK_INVERTED = 1'b0;
 169     parameter [4:0] IS_INMODE_INVERTED = 5'b0;
 170     parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
 171 endmodule
 172 """
 173 (* abc_box_id=3000 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT )
 174 (* abc_box_id=3001 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT_DPORT )
 175 (* abc_box_id=3002 *) `ABC_DSP48E1(\$__ABC_DSP48E1 )