1 # Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
3 # NB: Inputs/Outputs must be ordered alphabetically
4 # (with exceptions for carry in/out)
6 # Average across F7[AB]MUX
17 # Inputs: I0 I1 I2 I3 S
23 # CARRY4 + CARRY4_[ABCD]X
24 # Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
25 # Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3
26 # (NB: carry chain input/output must be last
27 # input/output and the entire bus has been
28 # moved there overriding the otherwise
29 # alphabetical ordering)
31 482 - - - - 223 - - - 222
32 598 407 - - - 400 205 - - 334
33 584 556 537 - - 523 558 226 - 239
34 642 615 596 438 - 582 618 330 227 313
35 536 379 - - - 340 - - - 271
36 494 465 445 - - 433 469 - - 157
37 592 540 520 356 - 512 548 292 - 228
38 580 526 507 398 385 508 528 378 380 114
41 # Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE
44 - - - - - - 631 472 407 238 127 - -
45 631 472 407 238 127 - - - - - - - -
48 # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
51 - - - - - - - 642 631 472 407 238 127 - -
52 642 631 472 407 238 127 - - - - - - - - -
54 # SLICEM/A6LUT + F7[AB]MUX
55 # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
58 - - - - - - - - 1009 998 839 774 605 494 450 - -
59 1047 1036 877 812 643 532 478 - - - - - - - - - -