techlibs/xilinx/abc_xc7.box

   1 # Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
   2 #                 https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf
   3
   4 # NB: Inputs/Outputs must be ordered alphabetically
   5 #     (with exceptions for carry in/out)
   6
   7 # Average across F7[AB]MUX
   8 # Inputs: I0 I1 S0
   9 # Outputs: O
  10 F7MUX 1 1 3 1
  11 204 208 286
  12
  13 # Inputs: I0 I1 S0
  14 # Outputs: O
  15 MUXF8 2 1 3 1
  16 104 94 273
  17
  18 # Box containing MUXF7.[AB] + MUXF8,
  19 #   Necessary to make these an atomic unit so that
  20 #   ABC cannot optimise just one of the MUXF7 away
  21 #   and expect to save on its delay
  22 # Inputs: I0 I1 I2 I3 S0 S1
  23 # Outputs: O
  24 $__MUXF78 3 1 6 1
  25 294 297 311 317 390 273
  26
  27 # CARRY4 + CARRY4_[ABCD]X
  28 # Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
  29 # Outputs:  O0 O1 O2 O3 CO0 CO1 CO2 CO3
  30 #   (NB: carry chain input/output must be last
  31 #        input/output and the entire bus has been
  32 #        moved there overriding the otherwise
  33 #        alphabetical ordering)
  34 CARRY4 4 1 10 8
  35 482 -   -   -   -   223 -   -   -   222
  36 598 407 -   -   -   400 205 -   -   334
  37 584 556 537 -   -   523 558 226 -   239
  38 642 615 596 438 -   582 618 330 227 313
  39 536 379 -   -   -   340 -   -   -   271
  40 494 465 445 -   -   433 469 -   -   157
  41 592 540 520 356 -   512 548 292 -   228
  42 580 526 507 398 385 508 528 378 380 114
  43
  44 # SLICEM/A6LUT
  45 # Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
  46 #   Necessary since RAMD* and SRL* have both combinatorial (i.e.
  47 #   same-cycle read operation) and sequential (write operation
  48 #   is only committed on the next clock edge).
  49 #   To model the combinatorial path, such cells have to be split
  50 #   into comb and seq parts, with this box modelling only the former.
  51 # Inputs: A S0 S1 S2 S3 S4 S5
  52 # Outputs: Y
  53 $__ABC_LUT6 2000 0 7 1
  54 0 642 631 472 407 238 127
  55
  56 # SLICEM/A6LUT + F7BMUX
  57 # Box to emulate comb/seq behaviour of RAMD128
  58 # Inputs: A S0 S1 S2 S3 S4 S5 S6
  59 # Outputs: DPO SPO
  60 $__ABC_LUT7 2001 0 8 1
  61 0 1047 1036 877 812 643 532 478