1 # Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
2 # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf
4 # NB: Inputs/Outputs must be ordered alphabetically
5 # (with exceptions for carry in/out)
7 # Average across F7[AB]MUX
18 # Box containing MUXF7.[AB] + MUXF8
19 # Inputs: I0 I1 I2 I3 S0 S1
22 294 297 311 317 390 273
24 # CARRY4 + CARRY4_[ABCD]X
25 # Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
26 # Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3
27 # (NB: carry chain input/output must be last
28 # input/output and the entire bus has been
29 # moved there overriding the otherwise
30 # alphabetical ordering)
32 482 - - - - 223 - - - 222
33 598 407 - - - 400 205 - - 334
34 584 556 537 - - 523 558 226 - 239
35 642 615 596 438 - 582 618 330 227 313
36 536 379 - - - 340 - - - 271
37 494 465 445 - - 433 469 - - 157
38 592 540 520 356 - 512 548 292 - 228
39 580 526 507 398 385 508 528 378 380 114
42 # Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
43 # Inputs: A S0 S1 S2 S3 S4 S5
45 $__ABC_LUT6 2000 0 7 1
46 0 642 631 472 407 238 127
48 # SLICEM/A6LUT + F7BMUX
49 # Box to emulate comb/seq behaviour of RAMD128
50 # Inputs: A S0 S1 S2 S3 S4 S5 S6
52 $__ABC_LUT7 2001 0 8 1
53 0 1047 1036 877 812 643 532 478