techlibs/xilinx/abc_xc7.box

   1 # Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
   2
   3 # NB: Inputs/Outputs must be ordered alphabetically
   4 #     (with exceptions for carry in/out)
   5
   6 # Average across F7[AB]MUX
   7 # Inputs: I0 I1 S0
   8 # Outputs: O
   9 F7MUX 1 1 3 1
  10 204 208 286
  11
  12 # Inputs: I0 I1 S0
  13 # Outputs: O
  14 MUXF8 2 1 3 1
  15 104 94 273
  16
  17 # Inputs: I0 I1 I2 I3 S0 S1
  18 # Outputs: O
  19 $__MUXF78 3 1 6 1
  20 294 297 311 317 390 273
  21
  22 # CARRY4 + CARRY4_[ABCD]X
  23 # Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
  24 # Outputs:  O0 O1 O2 O3 CO0 CO1 CO2 CO3
  25 #   (NB: carry chain input/output must be last
  26 #        input/output and the entire bus has been
  27 #        moved there overriding the otherwise
  28 #        alphabetical ordering)
  29 CARRY4 4 1 10 8
  30 482 -   -   -   -   223 -   -   -   222
  31 598 407 -   -   -   400 205 -   -   334
  32 584 556 537 -   -   523 558 226 -   239
  33 642 615 596 438 -   582 618 330 227 313
  34 536 379 -   -   -   340 -   -   -   271
  35 494 465 445 -   -   433 469 -   -   157
  36 592 540 520 356 -   512 548 292 -   228
  37 580 526 507 398 385 508 528 378 380 114
  38
  39 # SLICEM/A6LUT
  40 # Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE
  41 # Outputs: DPO SPO
  42 RAM32X1D 5 0 13 2
  43 -   -   -   -   -   - 631 472 407 238 127 - -
  44 631 472 407 238 127 - -   -   -   -   -   - -
  45
  46 # SLICEM/A6LUT
  47 # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
  48 # Outputs: DPO SPO
  49 RAM64X1D 6 0 15 2
  50 -   -   -   -   -   -   - 642 631 472 407 238 127 - -
  51 642 631 472 407 238 127 - -   -   -   -   -   -   - -
  52
  53 # SLICEM/A6LUT + F7[AB]MUX
  54 # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
  55 # Outputs: DPO SPO
  56 RAM128X1D 7 0 17 2
  57 -    -    -   -   -   -   -   - 1009 998 839 774 605 494 450 - -
  58 1047 1036 877 812 643 532 478 - -    -   -   -   -   -   -   - -
  59
  60 # Inputs: A S
  61 # Outputs: Y
  62 $__ABC_ASYNC 1000 0 2 1
  63 0 764
  64
  65 # Inputs: C CE D R \$pastQ
  66 # Outputs: Q
  67 FDRE 1001 1 5 1
  68 - 109 -46 358 0
  69
  70 # Inputs: C CE D R \$pastQ
  71 # Outputs: Q
  72 FDRE_1 1002 1 5 1
  73 - 109 -46 358 0
  74
  75 # Inputs: C CE CLR D \$pastQ
  76 # Outputs: Q
  77 FDCE 1003 1 5 1
  78 - 109 - -46 0
  79
  80 # Inputs: C CE CLR D \$pastQ
  81 # Outputs: Q
  82 FDCE_1004 1 1 5 1
  83 - 109 - -46 0
  84
  85 # Inputs: C CE D PRE \$pastQ
  86 # Outputs: Q
  87 FDPE 1005 1 5 1
  88 - 109 -46 - 0
  89
  90 # Inputs: C CE D PRE \$pastQ
  91 # Outputs: Q
  92 FDPE_1 1006 1 5 1
  93 - 109 -46 - 0