techlibs/xilinx/abc_xc7.box

   1 # Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
   2
   3 # NB: Inputs/Outputs must be ordered alphabetically
   4 #     (with exceptions for carry in/out)
   5
   6 # F7BMUX slower than F7AMUX
   7 # Inputs: I0 I1 S0
   8 # Outputs: O
   9 F7BMUX 1 1 3 1
  10 217 223 296
  11
  12 # Inputs: I0 I1 S0
  13 # Outputs: O
  14 MUXF8 2 1 3 1
  15 104 94 273
  16
  17 # CARRY4 + CARRY4_[ABCD]X
  18 # Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
  19 # Outputs:  O0 O1 O2 O3 CO0 CO1 CO2 CO3
  20 #   (NB: carry chain input/output must be last
  21 #        input/output and the entire bus has been
  22 #        moved there overriding the otherwise
  23 #        alphabetical ordering)
  24 CARRY4 3 1 10 8
  25 482 -   -   -   -   223 -   -   -   222
  26 598 407 -   -   -   400 205 -   -   334
  27 584 556 537 -   -   523 558 226 -   239
  28 642 615 596 438 -   582 618 330 227 313
  29 536 379 -   -   -   340 -   -   -   271
  30 494 465 445 -   -   433 469 -   -   157
  31 592 540 520 356 -   512 548 292 -   228
  32 580 526 507 398 385 508 528 378 380 114
  33
  34 # SLICEM/A6LUT
  35 # Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE
  36 # Outputs: DPO SPO
  37 RAM32X1D 4 0 13 2
  38 -   -   -   -   -   - 631 472 407 238 127 - -
  39 631 472 407 238 127 - -   -   -   -   -   - -
  40
  41 # SLICEM/A6LUT
  42 # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
  43 # Outputs: DPO SPO
  44 RAM64X1D 5 0 15 2
  45 -   -   -   -   -   -   - 642 631 472 407 238 127 - -
  46 642 631 472 407 238 127 - -   -   -   -   -   -   - -
  47
  48 # SLICEM/A6LUT + F7[AB]MUX
  49 # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
  50 # Outputs: DPO SPO
  51 RAM128X1D 6 0 17 2
  52 -    -    -   -   -   -   -   - 1009 998 839 774 605 494 450 - -
  53 1047 1036 877 812 643 532 478 - -    -   -   -   -   -   -   - -
  54
  55 # Inputs: C CE D R \$pastQ
  56 # Outputs: Q
  57 FDRE 7 1 5 1
  58 - 109 -46 358 0
  59
  60 # Inputs: C CE D S \$pastQ
  61 # Outputs: Q
  62 FDSE 8 0 5 1
  63 - 109 -46 358 0
  64
  65 # Inputs: C CE CLR D \$pastQ
  66 # Outputs: Q
  67 FDCE 9 0 5 1
  68 - 109 - -46 0
  69
  70 # Inputs: C CE D PRE \$pastQ
  71 # Outputs: Q
  72 FDPE 10 0 5 1
  73 - 109 -46 - 0