Carry in/out box ordering now move to end, not swap with end
[yosys.git] / techlibs / xilinx / abc_xc7.box
1 # Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
2
3 # F7BMUX slower than F7AMUX
4 # Inputs: I0 I1 S0
5 # Outputs: O
6 F7BMUX 1 1 3 1
7 217 223 296
8
9 # Inputs: I0 I1 S0
10 # Outputs: O
11 MUXF8 2 1 3 1
12 104 94 273
13
14 # CARRY4 + CARRY4_[ABCD]X
15 # Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
16 # Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3
17 # (NB: carry chain input/output must be last
18 # input/output and have been moved there
19 # overriding the alphabetical ordering)
20 CARRY4 3 1 10 8
21 482 - - - - 223 - - - 222
22 598 407 - - - 400 205 - - 334
23 584 556 537 - - 523 558 226 - 239
24 642 615 596 438 - 582 618 330 227 313
25 536 379 - - - 340 - - - 271
26 494 465 445 - - 433 469 - - 157
27 592 540 520 356 - 512 548 292 - 228
28 580 526 507 398 385 508 528 378 380 114